static int32_t sprdfb_dsi_set_hs_mode(void)
{
pr_debug(KERN_INFO "sprdfb: [%s]\n",__FUNCTION__);
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
return 0;
}
static int32_t sprdfb_dsi_set_lp_mode(void)
{
uint32_t reg_val;
pr_debug(KERN_INFO "sprdfb: [%s]\n",__FUNCTION__);
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x1fff);
reg_val = dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL);
reg_val = reg_val & (~(BIT(0)));
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, reg_val);
return 0;
}
static int32_t sprdfb_dsi_set_hs_mode(void)
{
pr_debug(KERN_INFO "sprdfb: [%s]\n",__FUNCTION__);
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
#ifdef FB_DSIH_VERSION_1P21A
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x0);
mipi_dsih_dphy_enable_hs_clk(&(dsi_ctx.dsi_inst.phy_instance), true);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
#endif
return 0;
}
static int32_t sprdfb_dsi_set_lp_mode(void)
{
uint32_t reg_val;
pr_debug(KERN_INFO "sprdfb: [%s]\n",__FUNCTION__);
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
#ifdef FB_DSIH_VERSION_1P21A
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x01ffff00);
mipi_dsih_dphy_enable_hs_clk(&(dsi_ctx.dsi_inst.phy_instance), false);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x1fff);
reg_val = dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL);
reg_val = reg_val & (~(BIT(0)));
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, reg_val);
#endif
return 0;
}
int32_t sprdfb_dsi_ready(struct sprdfb_device *dev)
{
struct info_mipi * mipi = dev->panel->info.mipi;
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_CMD_MODE_CFG, 0x1);
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_PHY_IF_CTRL, 0x1);
}else{
mipi_dsih_video_mode(&(dsi_ctx.dsi_inst), 1);
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_PWR_UP, 0);
udelay(100);
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_PWR_UP, 1);
udelay(10*1000);
dsi_core_read_function(DSI_CTL_BEGIN, R_DSI_HOST_ERROR_ST0);
dsi_core_read_function(DSI_CTL_BEGIN, R_DSI_HOST_ERROR_ST1);
}
return 0;
}
int32_t sprdfb_dsi_ready(struct sprdfb_device *dev)
{
struct info_mipi * mipi = dev->panel->info.mipi;
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
#ifdef FB_DSIH_VERSION_1P21A
mipi_dsih_dphy_enable_hs_clk(&(dsi_ctx.dsi_inst.phy_instance), true);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x0);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
#endif
}else{
#ifdef FB_DSIH_VERSION_1P21A
mipi_dsih_dphy_enable_hs_clk(&(dsi_ctx.dsi_inst.phy_instance), true);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
#endif
mipi_dsih_video_mode(&(dsi_ctx.dsi_inst), 1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PWR_UP, 0);
udelay(100);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PWR_UP, 1);
usleep_range(3000, 3500);
#ifdef FB_DSIH_VERSION_1P21A
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_ST0);
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_ST1);
#else
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_ST0);
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_ST1);
#endif
}
#ifdef FB_DSIH_VERSION_1P21A
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK0, 0x0);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK1, 0x800);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x0);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x800);
#endif
return 0;
}
static int32_t dsi_ready(struct panel_spec *panel)
{
struct info_mipi * mipi = panel->info.mipi;
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
mipi_dsih_cmd_mode(&(autotst_dsi_ctx.dsi_inst), 1);
#ifdef FB_DSIH_VERSION_1P21A
mipi_dsih_dphy_enable_hs_clk(&(autotst_dsi_ctx.dsi_inst.phy_instance), true);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
#endif
}else{
#ifdef FB_DSIH_VERSION_1P21A
mipi_dsih_dphy_enable_hs_clk(&(autotst_dsi_ctx.dsi_inst.phy_instance), true);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
#endif
mipi_dsih_video_mode(&(autotst_dsi_ctx.dsi_inst), 1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PWR_UP, 0);
udelay(100);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PWR_UP, 1);
mdelay(3);
#ifdef FB_DSIH_VERSION_1P21A
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_ST0);
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_ST1);
#else
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_ST0);
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_ST1);
#endif
}
#ifdef FB_DSIH_VERSION_1P21A
//dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK0, 0x0);
//dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK1, 0x800);
#else
//dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x0);
//dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x800);
#endif
return 0;
}
int32_t sprdfb_dsi_ready(struct sprdfb_device *dev)
{
struct info_mipi * mipi = dev->panel->info.mipi;
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_CMD_MODE_CFG, 0x1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
}else{
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_IF_CTRL, 0x1);
mipi_dsih_video_mode(&(dsi_ctx.dsi_inst), 1);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PWR_UP, 0);
udelay(100);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PWR_UP, 1);
hr_msleep(3);
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_ST0);
dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_ST1);
}
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x0);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x800);
return 0;
}
/**
* Send Generic READ command to peripheral
* @param instance pointer to structure holding the DSI Host core information
* @param vc destination virtual channel
* @param command generic command type
* @param lsb_byte first command parameter
* @param msb_byte second command parameter
* @param bytes_to_read no of bytes to read (expected to arrive at buffer)
* @param read_buffer pointer to 32-bit array to hold the read buffer words
* return read_buffer_length
* @note this function has an active delay to wait for the buffer to clear.
* The delay is limited to 2 x DSIH_FIFO_ACTIVE_WAIT
* (waiting for command buffer, and waiting for receiving)
* @note this function will enable BTA
*/
uint16_t mipi_dsih_gen_rd_cmd(dsih_ctrl_t * instance, uint8_t vc, uint8_t command, uint8_t msb_byte, uint8_t lsb_byte, uint8_t bytes_to_read, uint8_t* read_buffer)
{
dsih_error_t err_code = OK;
int timeout = 0;
int counter = 0;
int i = 0;
uint32_t temp[1] = {0};
if (instance == 0)
{
return 0;
}
if (instance->status != INITIALIZED)
{
return 0;
}
if (bytes_to_read < 1)
{
return 0;
}
if (read_buffer == 0)
{
return 0;
}
/* make sure command mode is on */
mipi_dsih_cmd_mode(instance, 1);
/* make sure receiving is enabled */
mipi_dsih_hal_bta_en(instance, 1);
/* listen to the same virtual channel as the one sent to */
mipi_dsih_hal_gen_rd_vc(instance, vc);
for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
{/* check if payload Tx fifo is not full */
if (!mipi_dsih_hal_gen_cmd_fifo_full(instance))
{
mipi_dsih_hal_gen_packet_header(instance, vc, command, msb_byte, lsb_byte);
break;
}
}
if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
{
err_code = 0;
}
/* loop for the number of words to be read */
for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
{ /* check if command transaction is done */
if (!mipi_dsih_hal_gen_rd_cmd_busy(instance))
{
for (counter = 0; counter < bytes_to_read; counter += 4)
{
err_code = mipi_dsih_hal_gen_read_payload(instance, temp);
if (err_code)
{
return 0;
}
for (i = 0; (i < 4) && ((counter + i) < bytes_to_read); i++)
{ /* put 32 bit temp in 4 bytes of buffer passed by user*/
read_buffer[counter + i] = (uint8_t)(temp[0] >> (i * 8));
}
}
}
}
return bytes_to_read;
}
/**
* Send a generic write command
* @param instance pointer to structure holding the DSI Host core information
* @param vc destination virtual channel
* @param command_type type of command, inserted in first byte of header
* @param params byte array of command parameters
* @param param_length length of the above array
* @return error code
* @note this function has an active delay to wait for the buffer to clear.
* The delay is limited to DSIH_FIFO_ACTIVE_WAIT
*/
dsih_error_t mipi_dsih_gen_wr_cmd(dsih_ctrl_t * instance, uint8_t vc, uint8_t command_type, uint8_t* params, uint16_t param_length)
{
dsih_error_t err_code = OK;
int timeout = 0;
int i = 0;
int j = 0;
int compliment_counter = 0;
uint8_t* payload = 0;
uint32_t temp = 0;
uint16_t word_count = 0;
if (instance == 0)
{
return ERR_DSI_INVALID_INSTANCE;
}
if (instance->status != INITIALIZED)
{
return ERR_DSI_INVALID_INSTANCE;
}
if (params == 0) /* NULL */
{
return ERR_DSI_OUT_OF_BOUND;
}
mipi_dsih_cmd_mode(instance, 1);
if (param_length > 2)
{
/* long packet - write the whole command to payload */
payload = params + (2 * sizeof(uint8_t));
word_count = (params[1] << 8) | params[0];
if ((param_length - 2) < word_count)
{
if (instance->log_error != 0)
{
instance->log_error("sent > input payload. complemented with zeroes");
}
compliment_counter = (param_length - 2) - word_count;
}
if ((param_length - 2) > word_count)
{
if (instance->log_error != 0)
{
instance->log_error("Overflow - input > sent. payload truncated");
}
}
for (i = 0; i < (param_length - 2); i += j)
{
temp = 0;
for (j = 0; (j < 4) && ((j + i) < (param_length - 2)); j++)
{
/* temp = (payload[i + 3] << 24) | (payload[i + 2] << 16) | (payload[i + 1] << 8) | payload[i]; */
temp |= payload[i + j] << (j * 8);
}
/* check if payload Tx fifo is not full */
for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT ; timeout++)
{
if (!mipi_dsih_hal_gen_packet_payload(instance, temp))
{
break;
}
}
if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
{
return ERR_DSI_TIMEOUT;
}
}
/* if word count entered by the user more than actual parameters received
* fill with zeroes - a fail safe mechanism, otherwise controller will
* want to send data from an empty buffer */
for (i = 0; i < compliment_counter; i++)
{
/* check if payload Tx fifo is not full */
for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT ; timeout++)
{
if (!mipi_dsih_hal_gen_packet_payload(instance, 0x00))
{
break;
}
}
if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
{
return ERR_DSI_TIMEOUT;
}
}
}
for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
{
/* check if payload Tx fifo is not full */
if (!mipi_dsih_hal_gen_cmd_fifo_full(instance))
{
if (param_length == 0)
{
err_code |= mipi_dsih_hal_gen_packet_header(instance, vc, command_type, 0x0, 0x0);
}
else if (param_length == 1)
{
err_code |= mipi_dsih_hal_gen_packet_header(instance, vc, command_type, 0x0, params[0]);
}
else
{
err_code |= mipi_dsih_hal_gen_packet_header(instance, vc, command_type, params[1], params[0]);
}
break;
}
}
if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
{
err_code = ERR_DSI_TIMEOUT;
}
return err_code;
}
static int32_t sprdfb_dsi_set_cmd_mode(void)
{
mipi_dsih_cmd_mode(&(dsi_ctx.dsi_inst), 1);
return 0;
}
