/* Configure MMC clock */ void clock_config_mmc(uint32_t interface, uint32_t freq) { uint32_t reg = 0; if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 ) { dprintf(CRITICAL, "Failure setting clock rate for MCLK - " "clk_rate: %d\n!", freq); ASSERT(0); } /* enable clock */ if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 ) { dprintf(CRITICAL, "Failure enabling MMC Clock!\n"); ASSERT(0); } reg |= MMC_BOOT_MCI_CLK_ENABLE; reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; writel( reg, MMC_BOOT_MCI_CLK ); /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ mmc_mclk_reg_wr_delay(); /* Wait 1 ms to provide the free running SD CLK to the card. */ mdelay(1); }
/* Configure MMC clock */ void clock_config_mmc(uint32_t interface, uint32_t freq) { int ret; uint32_t reg; char clk_name[64]; snprintf(clk_name, 64, "sdc%u_core_clk", interface); if(freq == MMC_CLK_400KHZ) { ret = clk_get_set_enable(clk_name, 400000, 1); } else if(freq == MMC_CLK_50MHZ) { ret = clk_get_set_enable(clk_name, 50000000, 1); } else { dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq); ASSERT(0); } if(ret) { dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret); ASSERT(0); } reg = 0; reg |= MMC_BOOT_MCI_CLK_ENABLE; reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; writel(reg, MMC_BOOT_MCI_CLK); /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ mmc_mclk_reg_wr_delay(); /* Wait 1 ms to provide the free running SD CLK to the card. */ mdelay(1); }