int mmc_go_idle(struct mmc_host *host)
{
int err;
struct mmc_command cmd = {0};
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_HIGH);
mmc_delay(1);
}
cmd.opcode = MMC_GO_IDLE_STATE;
cmd.arg = 0;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC;
err = mmc_wait_for_cmd(host, &cmd, 0);
mmc_delay(1);
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_DONTCARE);
mmc_delay(1);
}
host->use_spi_crc = 0;
return err;
}
int mmc_go_idle(struct mmc_host *host)
{
int err;
struct mmc_command cmd;
mmc_set_chip_select(host, MMC_CS_HIGH);
mmc_delay(1);
memset(&cmd, 0, sizeof(struct mmc_command));
cmd.opcode = MMC_GO_IDLE_STATE;
cmd.arg = 0;
cmd.flags = MMC_RSP_NONE | MMC_CMD_BC;
err = mmc_wait_for_cmd(host, &cmd, 0);
mmc_delay(1);
mmc_set_chip_select(host, MMC_CS_DONTCARE);
mmc_delay(1);
return err;
}
int mmc_go_idle(struct mmc_host *host)
{
int err;
struct mmc_command cmd;
/*
* Non-SPI hosts need to prevent chipselect going active during
* GO_IDLE; that would put chips into SPI mode. Remind them of
* that in case of hardware that won't pull up DAT3/nCS otherwise.
*
* SPI hosts ignore ios.chip_select; it's managed according to
* rules that must accomodate non-MMC slaves which this layer
* won't even know about.
*/
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_HIGH);
mmc_delay(1);
}
memset(&cmd, 0, sizeof(struct mmc_command));
cmd.opcode = MMC_GO_IDLE_STATE;
cmd.arg = 0;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC;
#if defined(CONFIG_AMBARELLA_IPC) && defined(CONFIG_MMC_AMBARELLA) && !defined(CONFIG_NOT_SHARE_SD_CONTROLLER_WITH_UITRON)
{
struct ipc_sdinfo *sdinfo = ambarella_sd_get_sdinfo(host);
if (sdinfo->from_ipc && !sdinfo->is_sdio) {
err = 0;
} else
err = mmc_wait_for_cmd(host, &cmd, 0);
}
#else
err = mmc_wait_for_cmd(host, &cmd, 0);
#endif
mmc_delay(1);
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_DONTCARE);
mmc_delay(1);
}
host->use_spi_crc = 0;
return err;
}
int mmc_go_idle(struct mmc_host *host)
{
int err;
struct mmc_command cmd;
DBG("[%s] s\n",__func__);
/*
* Non-SPI hosts need to prevent chipselect going active during
* GO_IDLE; that would put chips into SPI mode. Remind them of
* that in case of hardware that won't pull up DAT3/nCS otherwise.
*
* SPI hosts ignore ios.chip_select; it's managed according to
* rules that must accomodate non-MMC slaves which this layer
* won't even know about.
*/
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_HIGH);
mmc_delay(1);
}
memset(&cmd, 0, sizeof(struct mmc_command));
cmd.opcode = MMC_GO_IDLE_STATE;
cmd.arg = 0;
// cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC;
cmd.flags = MMC_RSP_NONE | MMC_CMD_BC; //zhf: mark SPI mode temporarily by James Tian
err = mmc_wait_for_cmd(host, &cmd, 0);
mmc_delay(1);
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_DONTCARE);
mmc_delay(1);
}
host->use_spi_crc = 0;
DBG("[%s] e\n",__func__);
return err;
}
int mmc_go_idle(struct mmc_host *host)
{
int err;
struct mmc_command cmd = {0};
#ifdef CONFIG_MMC_SDHCI_SCX35
unsigned int tmp_flag = 0, reg_val = 0;
#endif
/*
* Non-SPI hosts need to prevent chipselect going active during
* GO_IDLE; that would put chips into SPI mode. Remind them of
* that in case of hardware that won't pull up DAT3/nCS otherwise.
*
* SPI hosts ignore ios.chip_select; it's managed according to
* rules that must accommodate non-MMC slaves which this layer
* won't even know about.
*/
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_HIGH);
#ifdef CONFIG_MMC_SDHCI_SCX35
/* if sdio0 set data[3] to gpio out mode, and data is 1 , for shark*/
if ((host->pm_flags & MMC_PM_ONLY_USED_SDIO0_SHARK) != 0) {
tmp_flag = 0;
if ((sci_glb_raw_read(REG_AON_APB_APB_EB0) & BIT_GPIO_EB) == 0) {
sci_glb_set(REG_AON_APB_APB_EB0, BIT_GPIO_EB);
tmp_flag |= 1 << 0;
}
if ((sci_glb_raw_read(REG_AON_APB_APB_EB0) & BIT_PIN_EB) == 0) {
sci_glb_set(REG_AON_APB_APB_EB0, BIT_PIN_EB);
tmp_flag |= 1 << 1;
}
/* set sdio0 data[3] to gpio mode*/
reg_val = __raw_readl( SPRD_PIN_BASE + 0x1E0 );
__raw_writel( 0x30, SPRD_PIN_BASE + 0x1E0 );
/* set gpio output mode ,and out put 1 */
sci_glb_set((CTL_GPIO_BASE + 0x308), (1 << 4));
sci_glb_set((CTL_GPIO_BASE + 0x304), (1 << 4));
sci_glb_set((CTL_GPIO_BASE + 0x300), (1 << 4));
}
#endif
mmc_delay(1);
}
cmd.opcode = MMC_GO_IDLE_STATE;
cmd.arg = 0;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC;
err = mmc_wait_for_cmd(host, &cmd, 0);
mmc_delay(1);
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_DONTCARE);
#ifdef CONFIG_MMC_SDHCI_SCX35
/* if sdio0 set data[3] to gpio out mode, and data is 1 , for shark*/
if ((host->pm_flags & MMC_PM_ONLY_USED_SDIO0_SHARK) != 0) {
if ((tmp_flag & 1) != 0) {
sci_glb_clr(REG_AON_APB_APB_EB0, BIT_GPIO_EB);
}
if ((tmp_flag & (1 << 1)) != 0) {
sci_glb_clr(REG_AON_APB_APB_EB0, BIT_PIN_EB);
}
/* set sdio0 data[3] to sdio data pin*/
__raw_writel( reg_val, SPRD_PIN_BASE + 0x1E0 );
}
#endif
mmc_delay(1);
}
host->use_spi_crc = 0;
return err;
}
