static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) { struct mx6_mmdc_calibration calibration = {0}; mmdc_read_calibration(sysinfo, &calibration); debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); }
/* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM * - no variable global data is available */ void board_init_f(ulong dummy) { int errs; struct mx6_mmdc_calibration calibration = {0}; memset((void *)gd, 0, sizeof(struct global_data)); /* write leveling calibration defaults */ calibration.p0_mpwrdlctl = 0x40404040; calibration.p1_mpwrdlctl = 0x40404040; /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); SETUP_IOMUX_PADS(uart_pads); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); if (sysinfo.dsize != 1) { if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6SL)) { printf("cpu type 0x%x doesn't support 64-bit bus\n", get_cpu_type()); reset_cpu(0); } } #ifdef CONFIG_MX6SL mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs, &mx6sl_grp_ioregs); #else if (is_cpu_type(MXC_CPU_MX6Q)) { mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); } else { mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); } #endif mx6_dram_cfg(&sysinfo, &calibration, &ddrtype); errs = mmdc_do_write_level_calibration(&sysinfo); if (errs) { printf("error %d from write level calibration\n", errs); } else { errs = mmdc_do_dqs_calibration(&sysinfo); if (errs) { printf("error %d from dqs calibration\n", errs); } else { printf("completed successfully\n"); mmdc_read_calibration(&sysinfo, &calibration); display_calibration(&calibration); } } }