int spi_init_clk(void)
{
int pclk = module_get_clock(APB_CLK_BASE),
i, j;
for(i = 2; i < 255; i += 2)
for(j = 0; j < 256; j++)
if(pclk / (i * (j + 1)) <= SPI_CLK)
goto calc_finish;
calc_finish:
if(i >= 255 || j >= 256) {
printf("spi: calc clock failed(%d, %d), use default.\n", i, j);
i = 2; j = 39;
}
printf("PCLK: %d, PS: %d, SCR: %d, Fout: %d\n",
pclk, i, j, pclk / (i * (j + 1)));
writel(0, SSP_CR1_1);
writel(0, SSP_IMSC_1);
writel(i, SSP_CPSR_1);
writel((j << 8) | (3 << 6) | (0 << 4) | (7 << 0), SSP_CR0_1);
writel((1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), SSP_CR1_1);
return 0;
}
void tvif_set_clk(int num)
{
uint32_t val;
int clk;
if (num)
clk = module_get_clock("ids1-eitf");
else
clk = module_get_clock("ids0-eitf");
#ifndef CONFIG_COMPILE_FPGA
val = (1 << TVIF_CLK_CFG_EN_CLOCK) | (0 << TVIF_CLK_CFG_PB_CLOCK) |
(0 << TVIF_CLK_CFG_INV_CLOCK) | (1 << TVIF_CLK_CFG_SEL_CLOCK) |
((clk / 27000000 - 1) << TVIF_CLK_CFG_DIVER_CLOCK);
#else
val = (1 << TVIF_CLK_CFG_EN_CLOCK) | (0 << TVIF_CLK_CFG_PB_CLOCK) |
(0 << TVIF_CLK_CFG_INV_CLOCK) | (1 << TVIF_CLK_CFG_SEL_CLOCK) |
(0 << TVIF_CLK_CFG_DIVER_CLOCK);
#endif
tvif_writel(TVIF_CLK_CFG_ADDR, val, 0, 32);
}
