static void __init qemu_e500_setup_arch(void) { ppc_md.progress("qemu_e500_setup_arch()", 0); fsl_pci_init(); mpc85xx_smp_init(); }
static void __init qemu_e500_setup_arch(void) { ppc_md.progress("qemu_e500_setup_arch()", 0); fsl_pci_assign_primary(); swiotlb_detect_4g(); mpc85xx_smp_init(); }
/* * Setup the architecture */ void __init corenet_gen_setup_arch(void) { mpc85xx_smp_init(); swiotlb_detect_4g(); pr_info("%s board\n", ppc_md.name); mpc85xx_qe_init(); }
/* * Setup the architecture */ void __init corenet_gen_setup_arch(void) { mpc85xx_smp_init(); swiotlb_detect_4g(); pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); mpc85xx_qe_init(); }
/* * Setup the architecture */ static void __init panda_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("panda_setup_arch()", 0); mpc85xx_smp_init(); fsl_pci_assign_primary(); pr_info("Panda board from OCEDO\n"); }
/* * Setup the architecture */ static void __init mpc85xx_ds_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("mpc85xx_ds_setup_arch()", 0); swiotlb_detect_4g(); fsl_pci_assign_primary(); mpc85xx_ds_uli_init(); mpc85xx_smp_init(); printk("MPC85xx DS board from Freescale Semiconductor\n"); }
static void __init mpc85xx_mds_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("mpc85xx_mds_setup_arch()", 0); mpc85xx_smp_init(); mpc85xx_mds_qe_init(); fsl_pci_assign_primary(); swiotlb_detect_4g(); }
/* * Setup the architecture */ static void __init bsc913x_qds_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("bsc913x_qds_setup_arch()", 0); #if defined(CONFIG_SMP) mpc85xx_smp_init(); #endif fsl_pci_assign_primary(); pr_info("bsc913x board from Freescale Semiconductor\n"); }
/* * Setup the architecture */ void __init corenet_ds_setup_arch(void) { mpc85xx_smp_init(); #if defined(CONFIG_PCI) && defined(CONFIG_PPC64) pci_devs_phb_init(); #endif fsl_pci_assign_primary(); swiotlb_detect_4g(); pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); }
/* * Setup the architecture */ static void __init mpc85xx_rdb_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); mpc85xx_smp_init(); fsl_pci_assign_primary(); #ifdef CONFIG_QUICC_ENGINE mpc85xx_qe_init(); mpc85xx_qe_par_io_init(); #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) if (machine_is(p1025_rdb)) { struct device_node *np; struct ccsr_guts __iomem *guts; np = of_find_node_by_name(NULL, "global-utilities"); if (np) { guts = of_iomap(np, 0); if (!guts) { pr_err("mpc85xx-rdb: could not map global utilities register\n"); } else { /* P1025 has pins muxed for QE and other functions. To * enable QE UEC mode, we need to set bit QE0 for UCC1 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 * and QE12 for QE MII management singals in PMUXCR * register. */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); iounmap(guts); } of_node_put(np); } } #endif #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); }
static void __init mpc85xx_rds_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("p1023_rds_setup_arch()", 0); /* */ np = of_find_node_by_name(NULL, "bcsr"); if (np != NULL) { static u8 __iomem *bcsr_regs; bcsr_regs = of_iomap(np, 0); of_node_put(np); if (!bcsr_regs) { printk(KERN_ERR "BCSR: Failed to map bcsr register space\n"); return; } else { #define BCSR15_I2C_BUS0_SEG_CLR 0x07 #define BCSR15_I2C_BUS0_SEG2 0x02 /* */ #ifdef CONFIG_RTC_CLASS /* */ clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR); setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2); #endif iounmap(bcsr_regs); } } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,p1023-pcie") fsl_add_bridge(np, 0); #endif mpc85xx_smp_init(); }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc85xx_rds_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("p1023_rds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np != NULL) { static u8 __iomem *bcsr_regs; bcsr_regs = of_iomap(np, 0); of_node_put(np); if (!bcsr_regs) { printk(KERN_ERR "BCSR: Failed to map bcsr register space\n"); return; } else { #define BCSR15_I2C_BUS0_SEG_CLR 0x07 #define BCSR15_I2C_BUS0_SEG2 0x02 /* * Note: Accessing exclusively i2c devices. * * The i2c controller selects initially ID EEPROM in the u-boot; * but if menu configuration selects RTC support in the kernel, * the i2c controller switches to select RTC chip in the kernel. */ #ifdef CONFIG_RTC_CLASS /* Enable RTC chip on the segment #2 of i2c */ clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR); setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2); #endif iounmap(bcsr_regs); } } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,p1023-pcie") fsl_add_bridge(np, 0); #endif mpc85xx_smp_init(); }
/* * Setup the architecture */ static void __init p1022_rdk_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("p1022_rdk_setup_arch()", 0); #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock; diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port; #endif mpc85xx_smp_init(); fsl_pci_assign_primary(); swiotlb_detect_4g(); pr_info("Freescale / iVeia P1022 RDK reference board\n"); }
/* * Setup the architecture */ void __init corenet_gen_setup_arch(void) { mpc85xx_smp_init(); swiotlb_detect_4g(); #if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32) /* * Inbound windows don't cover the full lower 4 GiB * due to conflicts with PCICSRBAR and outbound windows, * so limit the DMA32 zone to 2 GiB, to allow consistent * allocations to succeed. */ limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT)); #endif pr_info("%s board\n", ppc_md.name); mpc85xx_qe_init(); }
/* * Setup the architecture */ static void __init p1022_ds_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("p1022_ds_setup_arch()", 0); #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) diu_ops.set_monitor_port = p1022ds_set_monitor_port; diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; /* * Disable the NOR and NAND flash nodes if there is video=fslfb... * command-line parameter. When the DIU is active, the localbus is * unavailable, so we have to disable these nodes before the MTD * driver loads. */ if (fslfb) { struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc"); if (np) { struct device_node *np2; of_node_get(np); np2 = of_find_compatible_node(np, NULL, "cfi-flash"); if (np2) { static struct property nor_status = { .name = "status", .value = "disabled", .length = sizeof("disabled"), }; /* * of_update_property() is called before * kmalloc() is available, so the 'new' object * should be allocated in the global area. * The easiest way is to do that is to * allocate one static local variable for each * call to this function. */ pr_info("p1022ds: disabling %s node", np2->full_name); of_update_property(np2, &nor_status); of_node_put(np2); } of_node_get(np); np2 = of_find_compatible_node(np, NULL, "fsl,elbc-fcm-nand"); if (np2) { static struct property nand_status = { .name = "status", .value = "disabled", .length = sizeof("disabled"), }; pr_info("p1022ds: disabling %s node", np2->full_name); of_update_property(np2, &nand_status); of_node_put(np2); } of_node_put(np); } } #endif mpc85xx_smp_init(); fsl_pci_assign_primary(); swiotlb_detect_4g(); #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) indirect_access_pixis_probe(); #endif pr_info("Freescale P1022 DS reference board\n"); } machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices); machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier); /* * Called very early, device-tree isn't unflattened */ static int __init p1022_ds_probe(void) { unsigned long root = of_get_flat_dt_root(); return of_flat_dt_is_compatible(root, "fsl,p1022ds"); } define_machine(p1022_ds) { .name = "P1022 DS", .probe = p1022_ds_probe, .setup_arch = p1022_ds_setup_arch, .init_IRQ = p1022_ds_pic_init, #ifdef CONFIG_PCI .pcibios_fixup_bus = fsl_pcibios_fixup_bus, .pcibios_fixup_phb = fsl_pcibios_fixup_phb, #endif .get_irq = mpic_get_irq, .restart = fsl_rstcr_restart, .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, };
/* ************************************************************************ * * Setup the architecture * */ static void __init twr_p1025_setup_arch(void) { #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("twr_p1025_setup_arch()", 0); mpc85xx_smp_init(); fsl_pci_assign_primary(); #ifdef CONFIG_QUICC_ENGINE np = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!np) { np = of_find_node_by_name(NULL, "qe"); if (!np) { printk(KERN_ERR "Could not find Quicc Engine node\n"); goto qe_fail; } } qe_reset(); of_node_put(np); np = of_find_node_by_name(NULL, "par_io"); if (np) { struct device_node *ucc; par_io_init(np); of_node_put(np); for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); } #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) if (machine_is(twr_p1025)) { struct ccsr_guts __iomem *guts; np = of_find_node_by_name(NULL, "global-utilities"); if (np) { guts = of_iomap(np, 0); if (!guts) pr_err("twr_p1025: could not map global utilities register\n"); else { /* P1025 has pins muxed for QE and other functions. To * enable QE UEC mode, we need to set bit QE0 for UCC1 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 * and QE12 for QE MII management signals in PMUXCR * register. */ printk(KERN_INFO "P1025 pinmux configured for QE\n"); /* Set QE mux bits in PMUXCR */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); iounmap(guts); #if defined(CONFIG_SERIAL_QE) || defined(CONFIG_SERIAL_QE_MODULE) /* On P1025TWR board, the UCC7 acted as UART port. * However, The UCC7's CTS pin is low level in default, * it will impact the transmission in full duplex * communication. So disable the Flow control pin PA18. * The UCC7 UART just can use RXD and TXD pins. */ par_io_config_pin(0, 18, 0, 0, 0, 0); #endif /* Drive PB29 to CPLD low - CPLD will then change * muxing from LBC to QE */ par_io_config_pin(1, 29, 1, 0, 0, 0); par_io_data_set(1, 29, 0); } of_node_put(np); } } #endif qe_fail: #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "TWR-P1025 board from Freescale Semiconductor\n"); }
/* * Setup the architecture */ static void __init mpc85xx_rdb_setup_arch(void) { #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif #if defined(CONFIG_QUICC_ENGINE) && defined(CONFIG_SPI_FSL_SPI) struct device_node *qe_spi; #endif struct ccsr_guts __iomem *guts; if (ppc_md.progress) ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); mpc85xx_smp_init(); fsl_pci_assign_primary(); #ifdef CONFIG_QUICC_ENGINE np = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!np) { pr_err("%s: Could not find Quicc Engine node\n", __func__); goto qe_fail; } qe_reset(); of_node_put(np); np = of_find_node_by_name(NULL, "par_io"); if (np) { struct device_node *ucc; par_io_init(np); of_node_put(np); for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); /* To P1025 QE/TDM, the name of ucc nodes is "tdm@xxxx" */ for_each_node_by_name(ucc, "tdm") par_io_of_config(ucc); #ifdef CONFIG_SPI_FSL_SPI for_each_node_by_name(qe_spi, "spi") par_io_of_config(qe_spi); #endif /* CONFIG_SPI_FSL_SPI */ } np = of_find_node_by_name(NULL, "global-utilities"); if (np) { guts = of_iomap(np, 0); if (!guts) pr_err("mpc85xx-rdb: could not map global " "utilities register\n"); else { #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) if (machine_is(p1025_rdb)) { /* * P1025 has pins muxed for QE and other * functions. To enable QE UEC mode, we * need to set bit QE0 for UCC1 in Eth mode, * QE0 and QE3 for UCC5 in Eth mode, QE9 * and QE12 for QE MII management singals * in PMUXCR register. */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); } #endif #ifdef CONFIG_FSL_UCC_TDM if (machine_is(p1021_rdb_pc) || machine_is(p1025_rdb)) { /* Clear QE12 for releasing the LBCTL */ clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); /* TDMA */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(5) | MPC85xx_PMUXCR_QE(11)); /* TDMB */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(9)); /* TDMC */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0)); /* TDMD */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(8) | MPC85xx_PMUXCR_QE(7)); } #endif /* CONFIG_FSL_UCC_TDM */ #ifdef CONFIG_SPI_FSL_SPI if (of_find_compatible_node(NULL, NULL, "fsl,mpc8569-qe-spi")) { clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); /*QE-SPI*/ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(6) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(10)); } #endif /* CONFIG_SPI_FSL_SPI */ iounmap(guts); } of_node_put(np); } qe_fail: #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); }