void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
{
const struct mrc_saved_data *mrc_cache;
struct FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
int prev_sleep_state = chipset_prev_sleep_state(ps);
fill_console_params(mupd);
mainboard_memory_init_params(mupd);
/* Do NOT let FSP do any GPIO pad configuration */
mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL;
/* Reserve enough memory under TOLUD to save CBMEM header */
mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size();
/*
* FSPM_UPD passed here is populated with default values provided by
* the blob itself. We let FSPM use top of CAR region of the size it
* requests.
* TODO: add checks to avoid overlap/conflict of CAR usage.
*/
mupd->FspmArchUpd.StackBase = _car_region_end -
mupd->FspmArchUpd.StackSize;
arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) {
/* MRC cache found */
arch_upd->NvsBufferPtr = (void *)mrc_cache->data;
arch_upd->BootMode =
prev_sleep_state == SLEEP_STATE_S3 ?
FSP_BOOT_ON_S3_RESUME:
FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n",
mrc_cache->size, arch_upd->BootMode);
} else
printk(BIOS_DEBUG, "MRC cache was not found\n");
}
}
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
const struct mrc_saved_data *cache;
struct romstage_handoff *handoff;
struct pei_data *pei_data;
post_code(0x32);
timestamp_add_now(TS_BEFORE_INITRAM);
pei_data = params->pei_data;
pei_data->boot_mode = params->power_state->prev_sleep_state;
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
if (params->power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
/* Perform remaining SOC initialization */
soc_pre_ram_init(params);
post_code(0x33);
/* Check recovery and MRC cache */
params->pei_data->saved_data_size = 0;
params->pei_data->saved_data = NULL;
if (!params->pei_data->disable_saved_data) {
if (vboot_recovery_mode_enabled()) {
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG,
"Recovery mode: not using MRC cache.\n");
} else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)
&& (!mrc_cache_get_current_with_version(&cache,
params->fsp_version))) {
/* MRC cache found */
params->pei_data->saved_data_size = cache->size;
params->pei_data->saved_data = &cache->data[0];
} else if (params->pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
hard_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
mainboard_check_ec_image(params);
}
}
/* Initialize RAM */
raminit(params);
timestamp_add_now(TS_AFTER_INITRAM);
/* Save MRC output */
if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
pei_data->data_to_save, pei_data->data_to_save_size);
if ((params->pei_data->boot_mode != ACPI_S3)
&& (params->pei_data->data_to_save_size != 0)
&& (params->pei_data->data_to_save != NULL))
mrc_cache_stash_data_with_version(
params->pei_data->data_to_save,
params->pei_data->data_to_save_size,
params->fsp_version);
}
/* Save DIMM information */
mainboard_save_dimm_info(params);
/* Create romstage handof information */
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (params->power_state->prev_sleep_state ==
ACPI_S3);
else {
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
hard_reset();
}
/*
* Initialize the TPM, unless the TPM was already initialized
* in verstage and used to verify romstage.
*/
if (IS_ENABLED(CONFIG_LPC_TPM) &&
!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
!IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
init_tpm(params->power_state->prev_sleep_state ==
ACPI_S3);
}
