static void quark_enable_legacy_seg(void) { u32 hmisc2; hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2); hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2); }
static void quark_setup_bars(void) { /* GPIO - D31:F0:R44h */ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, CONFIG_GPIO_BASE | IO_BAR_EN); /* ACPI PM1 Block - D31:F0:R48h */ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, CONFIG_ACPI_PM1_BASE | IO_BAR_EN); /* GPE0 - D31:F0:R4Ch */ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); /* WDT - D31:F0:R84h */ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, CONFIG_WDT_BASE | IO_BAR_EN); /* RCBA - D31:F0:RF0h */ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, CONFIG_RCBA_BASE | MEM_BAR_EN); /* ACPI P Block - Msg Port 04:R70h */ msg_port_write(MSG_PORT_RMU, PBLK_BA, CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); /* SPI DMA - Msg Port 04:R7Ah */ msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, CONFIG_SPI_DMA_BASE | IO_BAR_EN); /* PCIe ECAM */ msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); }
static void quark_setup_mtrr(void) { u32 base, mask; int i; disable_caches(); /* mark the VGA RAM area as uncacheable */ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000, MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000, MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); /* mark other fixed range areas as cacheable */ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000, MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000, MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000, MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000, MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++) msg_port_write(MSG_PORT_HOST_BRIDGE, i, MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); /* variable range MTRR#0: ROM area */ mask = ~(CONFIG_SYS_MONITOR_LEN - 1); base = CONFIG_SYS_TEXT_BASE & mask; msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), base | MTRR_TYPE_WRBACK); msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM), mask | MTRR_PHYS_MASK_VALID); /* variable range MTRR#1: eSRAM area */ mask = ~(ESRAM_SIZE - 1); base = CONFIG_ESRAM_BASE & mask; msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), base | MTRR_TYPE_WRBACK); msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM), mask | MTRR_PHYS_MASK_VALID); /* enable both variable and fixed range MTRRs */ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE, MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN); enable_caches(); }