static int msm_csid_config(struct csid_cfg_params *cfg_params) { int rc = 0; uint32_t val = 0; struct csid_device *csid_dev; struct msm_camera_csid_params *csid_params; void __iomem *csidbase; csid_dev = v4l2_get_subdevdata(cfg_params->subdev); csidbase = csid_dev->base; if (csidbase == NULL) return -ENOMEM; csid_params = cfg_params->parms; val = csid_params->lane_cnt - 1; val |= csid_params->lane_assign << 2; val |= 0x1 << 10; val |= 0x1 << 11; val |= 0x1 << 12; val |= 0x1 << 13; val |= 0x1 << 28; msm_io_w(val, csidbase + CSID_CORE_CTRL_ADDR); rc = msm_csid_cid_lut(&csid_params->lut_params, csidbase); if (rc < 0) return rc; msm_csid_set_debug_reg(csidbase, csid_params); return rc; }
static int msm_csid_config(struct csid_device *csid_dev, struct msm_camera_csid_params *csid_params) { int rc = 0; uint32_t val = 0; void __iomem *csidbase; csidbase = csid_dev->base; if (!csidbase || !csid_params) { pr_err("%s:%d csidbase %p, csid params %p\n", __func__, __LINE__, csidbase, csid_params); return -EINVAL; } CDBG("%s csid_params, lane_cnt = %d, lane_assign = 0x%x\n", __func__, csid_params->lane_cnt, csid_params->lane_assign); CDBG("%s csid_params phy_sel = %d\n", __func__, csid_params->phy_sel); msm_csid_reset(csid_dev); val = csid_params->lane_cnt - 1; val |= csid_params->lane_assign << csid_dev->ctrl_reg->csid_reg.csid_dl_input_sel_shift; if (csid_dev->hw_version < 0x30000000) { val |= (0xF << 10); msm_camera_io_w(val, csidbase + csid_dev->ctrl_reg->csid_reg.csid_core_ctrl_0_addr); } else { msm_camera_io_w(val, csidbase + csid_dev->ctrl_reg->csid_reg.csid_core_ctrl_0_addr); val = csid_params->phy_sel << csid_dev->ctrl_reg->csid_reg.csid_phy_sel_shift; val |= 0xF; msm_camera_io_w(val, csidbase + csid_dev->ctrl_reg->csid_reg.csid_core_ctrl_1_addr); } rc = msm_csid_cid_lut(&csid_params->lut_params, csid_dev); if (rc < 0) return rc; msm_csid_set_debug_reg(csid_dev, csid_params); return rc; }
static int msm_csid_config(struct csid_device *csid_dev, struct msm_camera_csid_params *csid_params) { int rc = 0; uint32_t val = 0; void __iomem *csidbase; csidbase = csid_dev->base; if (!csidbase || !csid_params) { pr_err("%s:%d csidbase %p, csid params %p\n", __func__, __LINE__, csidbase, csid_params); return -EINVAL; } CDBG("%s csid_params, lane_cnt = %d, lane_assign = %x, phy sel = %d\n", __func__, csid_params->lane_cnt, csid_params->lane_assign, csid_params->phy_sel); msm_csid_reset(csid_dev); val = csid_params->lane_cnt - 1; val |= csid_params->lane_assign << CSID_DL_INPUT_SEL_SHIFT; if (csid_dev->hw_version < 0x30000000) { val |= (0xF << 10); msm_camera_io_w(val, csidbase + CSID_CORE_CTRL_0_ADDR); } else { msm_camera_io_w(val, csidbase + CSID_CORE_CTRL_0_ADDR); val = csid_params->phy_sel << CSID_PHY_SEL_SHIFT; val |= 0xF; msm_camera_io_w(val, csidbase + CSID_CORE_CTRL_1_ADDR); } rc = msm_csid_cid_lut(&csid_params->lut_params, csidbase); if (rc < 0) return rc; msm_csid_set_debug_reg(csidbase, csid_params); return rc; }
static int msm_csid_config(struct csid_device *csid_dev, struct msm_camera_csid_params *csid_params) { int rc = 0; uint32_t val = 0, clk_rate = 0, round_rate = 0; struct clk **csid_clk_ptr; void __iomem *csidbase; csidbase = csid_dev->base; if (!csidbase || !csid_params) { pr_err("%s:%d csidbase %p, csid params %p\n", __func__, __LINE__, csidbase, csid_params); return -EINVAL; } CDBG("%s csid_params, lane_cnt = %d, lane_assign = 0x%x\n", __func__, csid_params->lane_cnt, csid_params->lane_assign); CDBG("%s csid_params phy_sel = %d\n", __func__, csid_params->phy_sel); csid_dev->csid_lane_cnt = csid_params->lane_cnt; msm_csid_reset(csid_dev); csid_clk_ptr = csid_dev->csid_clk; if (!csid_clk_ptr) { pr_err("csi_src_clk get failed\n"); return -EINVAL; } clk_rate = (csid_params->csi_clk > 0) ? (csid_params->csi_clk) : csid_dev->csid_max_clk; round_rate = clk_round_rate(csid_clk_ptr[csid_dev->csid_clk_index], clk_rate); if (round_rate > csid_dev->csid_max_clk) round_rate = csid_dev->csid_max_clk; pr_debug("usr set rate csi_clk clk_rate = %u round_rate = %u\n", clk_rate, round_rate); rc = clk_set_rate(csid_clk_ptr[csid_dev->csid_clk_index], round_rate); if (rc < 0) { pr_err("csi_src_clk set failed\n"); return rc; } val = csid_params->lane_cnt - 1; val |= csid_params->lane_assign << csid_dev->ctrl_reg->csid_reg.csid_dl_input_sel_shift; if (csid_dev->hw_version < 0x30000000) { val |= (0xF << 10); msm_camera_io_w(val, csidbase + csid_dev->ctrl_reg->csid_reg.csid_core_ctrl_0_addr); } else { msm_camera_io_w(val, csidbase + csid_dev->ctrl_reg->csid_reg.csid_core_ctrl_0_addr); val = csid_params->phy_sel << csid_dev->ctrl_reg->csid_reg.csid_phy_sel_shift; val |= 0xF; msm_camera_io_w(val, csidbase + csid_dev->ctrl_reg->csid_reg.csid_core_ctrl_1_addr); } rc = msm_csid_cid_lut(&csid_params->lut_params, csid_dev); if (rc < 0) return rc; msm_csid_set_debug_reg(csid_dev, csid_params); return rc; }