/*
* Prepare interrupt subsystem for entering sleep -- phase 2.
* Detect any pending interrupts and configure interrupt hardware.
*
* Return value:
* -EAGAIN: there are pending interrupt(s); interrupt configuration
* is not changed.
* 0: success
*/
int msm_irq_enter_sleep2(bool modem_wake, int from_idle)
{
int i, limit = 10;
uint32_t pending[VIC_NUM_REGS];
if (from_idle && !modem_wake)
return 0;
/* edge triggered interrupt may get lost if this mode is used */
WARN_ON_ONCE(!modem_wake && !from_idle);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
DPRINT_REGS(VIC_IRQ_STATUS, "%s change irq, pend", __func__);
for (i = 0; i < VIC_NUM_REGS; i++) {
pending[i] = readl(VIC_IRQ_STATUS0 + (i * 4));
pending[i] &= msm_irq_shadow_reg[i].int_en[!from_idle];
}
/*
* Clear INT_A9_M2A_5 since requesting sleep triggers it.
* In some arch e.g. FSM9XXX, INT_A9_M2A_5 may not be in the first set.
*/
pending[INT_A9_M2A_5 / 32] &= ~(1U << (INT_A9_M2A_5 % 32));
for (i = 0; i < VIC_NUM_REGS; i++) {
if (pending[i]) {
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
DPRINT_ARRAY(pending, "%s abort",
__func__);
return -EAGAIN;
}
}
msm_irq_write_all_regs(VIC_INT_EN0, 0);
while (limit-- > 0) {
int pend_irq;
int irq = readl(VIC_IRQ_VEC_RD);
if (irq == -1)
break;
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
printk(KERN_INFO "%s cleared int %d (%d)\n",
__func__, irq, pend_irq);
}
if (modem_wake) {
msm_irq_set_type(INT_A9_M2A_6, IRQF_TRIGGER_RISING);
__raw_writel(1U << (INT_A9_M2A_6 % 32),
VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, INT_A9_M2A_6));
} else {
for (i = 0; i < VIC_NUM_REGS; i++)
writel(msm_irq_shadow_reg[i].int_en[1],
VIC_INT_ENSET0 + (i * 4));
}
dsb();
return 0;
}
int msm_irq_enter_sleep2(bool modem_wake, int from_idle)
{
int i, limit = 10;
uint32_t pending[VIC_NUM_REGS];
if (from_idle && !modem_wake)
return 0;
/* */
WARN_ON_ONCE(!modem_wake && !from_idle);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
DPRINT_REGS(VIC_IRQ_STATUS, "%s change irq, pend", __func__);
for (i = 0; i < VIC_NUM_REGS; i++) {
pending[i] = readl(VIC_IRQ_STATUS0 + (i * 4));
pending[i] &= msm_irq_shadow_reg[i].int_en[!from_idle];
}
/*
*/
pending[INT_A9_M2A_5 / 32] &= ~(1U << (INT_A9_M2A_5 % 32));
for (i = 0; i < VIC_NUM_REGS; i++) {
if (pending[i]) {
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
DPRINT_ARRAY(pending, "%s abort",
__func__);
return -EAGAIN;
}
}
msm_irq_write_all_regs(VIC_INT_EN0, 0);
while (limit-- > 0) {
int pend_irq;
int irq = readl(VIC_IRQ_VEC_RD);
if (irq == -1)
break;
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
printk(KERN_INFO "%s cleared int %d (%d)\n",
__func__, irq, pend_irq);
}
if (modem_wake) {
struct irq_data d = { .irq = INT_A9_M2A_6 };
msm_irq_set_type(&d, IRQF_TRIGGER_RISING);
__raw_writel(1U << (INT_A9_M2A_6 % 32),
VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, INT_A9_M2A_6));
} else {
for (i = 0; i < VIC_NUM_REGS; i++)
/*
* Prepare interrupt subsystem for entering sleep -- phase 2.
* Detect any pending interrupts and configure interrupt hardware.
*
* Return value:
* -EAGAIN: there are pending interrupt(s); interrupt configuration
* is not changed.
* 0: success
*/
int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
{
int limit = 10;
uint32_t pending0, pending1;
if (from_idle && !arm9_wake)
return 0;
/* edge triggered interrupt may get lost if this mode is used */
WARN_ON_ONCE(!arm9_wake && !from_idle);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
printk(KERN_INFO "%s change irq, pend %x %x\n", __func__,
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
pending0 = readl(VIC_IRQ_STATUS0);
pending1 = readl(VIC_IRQ_STATUS1);
pending0 &= msm_irq_shadow_reg[0].int_en[!from_idle];
/* Clear INT_A9_M2A_5 since requesting sleep triggers it */
pending0 &= ~((1U << INT_A9_M2A_5) | (1U << INT_A9_M2A_3));
pending1 &= msm_irq_shadow_reg[1].int_en[!from_idle];
if (pending0 || pending1) {
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
printk(KERN_INFO "%s abort %x %x\n", __func__,
pending0, pending1);
return -EAGAIN;
}
writel(0, VIC_INT_EN0);
writel(0, VIC_INT_EN1);
while (limit-- > 0) {
int pend_irq;
int irq = readl(VIC_IRQ_VEC_RD);
if (irq == -1)
break;
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
printk(KERN_INFO "%s cleared int %d (%d)\n",
__func__, irq, pend_irq);
}
if (arm9_wake) {
msm_irq_set_type(INT_A9_M2A_6, IRQF_TRIGGER_RISING);
writel(1U << INT_A9_M2A_6, VIC_INT_ENSET0);
} else {
writel(msm_irq_shadow_reg[0].int_en[1], VIC_INT_ENSET0);
writel(msm_irq_shadow_reg[1].int_en[1], VIC_INT_ENSET1);
}
return 0;
}
int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
{
int limit = 10;
uint32_t pending0, pending1;
if (from_idle && !arm9_wake)
return 0;
WARN_ON_ONCE(!arm9_wake && !from_idle);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
printk(KERN_INFO "msm_irq_enter_sleep change irq, pend %x %x\n",
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
pending0 = readl(VIC_IRQ_STATUS0);
pending1 = readl(VIC_IRQ_STATUS1);
pending0 &= msm_irq_shadow_reg[0].int_en[!from_idle];
pending0 &= ~(1U << INT_A9_M2A_5);
pending1 &= msm_irq_shadow_reg[1].int_en[!from_idle];
if (pending0 || pending1) {
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
printk(KERN_INFO "msm_irq_enter_sleep2 abort %x %x\n",
pending0, pending1);
return -EAGAIN;
}
writel(0, VIC_INT_EN0);
writel(0, VIC_INT_EN1);
while (limit-- > 0) {
int pend_irq;
int irq = readl(VIC_IRQ_VEC_RD);
if (irq == -1)
break;
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
printk(KERN_INFO "msm_irq_enter_sleep cleared "
"int %d (%d)\n", irq, pend_irq);
}
if (arm9_wake) {
msm_irq_set_type(INT_A9_M2A_6, IRQF_TRIGGER_RISING);
msm_irq_ack(INT_A9_M2A_6);
writel(1U << INT_A9_M2A_6, VIC_INT_ENSET0);
} else {
writel(msm_irq_shadow_reg[0].int_en[1], VIC_INT_ENSET0);
writel(msm_irq_shadow_reg[1].int_en[1], VIC_INT_ENSET1);
}
return 0;
}
int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
{
int limit = 10;
uint32_t pending[VIC_NUM_BANKS];
int i;
uint32_t any = 0;
if (from_idle && !arm9_wake)
return 0;
/* edge triggered interrupt may get lost if this mode is used */
WARN_ON_ONCE(!arm9_wake && !from_idle);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP) {
printk(KERN_INFO "%s: change irq, pend", __func__);
print_vic_irq_stat();
}
for (i = 0; i < VIC_NUM_BANKS; ++i) {
pending[i] = readl(VIC_IRQ_STATUS(i));
pending[i] &= msm_irq_shadow_reg[i].int_en[!from_idle];
/* Clear INT_A9_M2A_5 since requesting sleep triggers it */
if (i == (INT_A9_M2A_5 / 32))
pending[i] &= ~(1U << (INT_A9_M2A_5 % 32));
any |= pending[i];
}
if (any) {
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT) {
printk(KERN_INFO "%s abort", __func__);
print_irq_array(pending, VIC_NUM_BANKS);
}
return -EAGAIN;
}
for (i = 0; i < VIC_NUM_BANKS; ++i)
writel(0, VIC_INT_EN(i));
while (limit-- > 0) {
int pend_irq;
int irq = readl(VIC_IRQ_VEC_RD);
if (irq == -1)
break;
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
printk(KERN_INFO "msm_irq_enter_sleep cleared "
"int %d (%d)\n", irq, pend_irq);
}
if (arm9_wake) {
msm_irq_set_type(INT_A9_M2A_6, IRQF_TRIGGER_RISING);
msm_irq_ack(INT_A9_M2A_6);
writel(1U << INT_A9_M2A_6, VIC_INT_ENSET(0));
} else {
for (i = 0; i < VIC_NUM_BANKS; ++i)
writel(msm_irq_shadow_reg[i].int_en[1],
VIC_INT_ENSET(i));
}
return 0;
}
