static int msm_sata_clk_init(struct device *dev)
{
	int ret = 0;
	struct msm_sata_hba *hba = dev_get_drvdata(dev);

	
	ret = msm_sata_clk_get_prepare_enable(dev,
			"slave_iface_clk", &hba->slave_iface_clk);
	if (ret)
		goto out;

	
	ret = msm_sata_clk_get_prepare_enable(dev,
			"iface_clk", &hba->iface_clk);
	if (ret)
		goto put_dis_slave_iface_clk;

	
	ret = msm_sata_clk_get_prepare_enable(dev,
			"bus_clk", &hba->bus_clk);
	if (ret)
		goto put_dis_iface_clk;

	
	ret = msm_sata_clk_get_prepare_enable_set_rate(dev,
			"src_clk", &hba->src_clk, 100000000);
	if (ret)
		goto put_dis_bus_clk;

	ret = msm_sata_clk_get_prepare_enable(dev,
			"core_rxoob_clk", &hba->rxoob_clk);
	if (ret)
		goto put_dis_src_clk;

	ret = msm_sata_clk_get_prepare_enable(dev,
			"core_pmalive_clk", &hba->pmalive_clk);
	if (ret)
		goto put_dis_rxoob_clk;

	
	ret = msm_sata_clk_get_prepare_enable(dev,
			"cfg_clk", &hba->cfg_clk);
	if (ret)
		goto put_dis_pmalive_clk;

	return ret;

put_dis_pmalive_clk:
	msm_sata_clk_put_unprepare_disable(&hba->pmalive_clk);
put_dis_rxoob_clk:
	msm_sata_clk_put_unprepare_disable(&hba->rxoob_clk);
put_dis_src_clk:
	msm_sata_clk_put_unprepare_disable(&hba->src_clk);
put_dis_bus_clk:
	msm_sata_clk_put_unprepare_disable(&hba->bus_clk);
put_dis_iface_clk:
	msm_sata_clk_put_unprepare_disable(&hba->iface_clk);
put_dis_slave_iface_clk:
	msm_sata_clk_put_unprepare_disable(&hba->slave_iface_clk);
out:
	return ret;
}
Exemple #2
0
static int msm_sata_clk_init(struct device *dev)
{
	int ret = 0;
	struct msm_sata_hba *hba = dev_get_drvdata(dev);

	/* Enable AHB clock for system fabric slave port connected to SATA */
	ret = msm_sata_clk_get_prepare_enable(dev,
			"slave_iface_clk", &hba->slave_iface_clk);
	if (ret)
		goto out;

	/* Enable AHB clock for system fabric and SATA core interface */
	ret = msm_sata_clk_get_prepare_enable(dev,
			"iface_clk", &hba->iface_clk);
	if (ret)
		goto put_dis_slave_iface_clk;

	/* Enable AXI clock for SATA AXI master and slave interfaces */
	ret = msm_sata_clk_get_prepare_enable(dev,
			"bus_clk", &hba->bus_clk);
	if (ret)
		goto put_dis_iface_clk;

	/* Enable the source clock for pmalive, rxoob and phy ref clocks */
	ret = msm_sata_clk_get_prepare_enable_set_rate(dev,
			"src_clk", &hba->src_clk, 100000000);
	if (ret)
		goto put_dis_bus_clk;

	/*
	 * Enable RX OOB detection clock. The clock rate is
	 * same as PHY reference clock (100MHz).
	 */
	ret = msm_sata_clk_get_prepare_enable(dev,
			"core_rxoob_clk", &hba->rxoob_clk);
	if (ret)
		goto put_dis_src_clk;

	/*
	 * Enable power management always-on clock. The clock rate
	 * is same as PHY reference clock (100MHz).
	 */
	ret = msm_sata_clk_get_prepare_enable(dev,
			"core_pmalive_clk", &hba->pmalive_clk);
	if (ret)
		goto put_dis_rxoob_clk;

	/* Enable PHY configuration AHB clock, fixed 64MHz clock */
	ret = msm_sata_clk_get_prepare_enable(dev,
			"cfg_clk", &hba->cfg_clk);
	if (ret)
		goto put_dis_pmalive_clk;

	return ret;

put_dis_pmalive_clk:
	msm_sata_clk_put_unprepare_disable(&hba->pmalive_clk);
put_dis_rxoob_clk:
	msm_sata_clk_put_unprepare_disable(&hba->rxoob_clk);
put_dis_src_clk:
	msm_sata_clk_put_unprepare_disable(&hba->src_clk);
put_dis_bus_clk:
	msm_sata_clk_put_unprepare_disable(&hba->bus_clk);
put_dis_iface_clk:
	msm_sata_clk_put_unprepare_disable(&hba->iface_clk);
put_dis_slave_iface_clk:
	msm_sata_clk_put_unprepare_disable(&hba->slave_iface_clk);
out:
	return ret;
}