static int krait_release_secondary(unsigned long base, int cpu)
{
void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);
if (!base_ptr)
return -ENODEV;
msm_spm_turn_on_cpu_rail(cpu);
writel_relaxed(0x109, base_ptr+0x04);
writel_relaxed(0x101, base_ptr+0x04);
ndelay(300);
writel_relaxed(0x121, base_ptr+0x04);
udelay(2);
writel_relaxed(0x020, base_ptr+0x04);
udelay(2);
writel_relaxed(0x000, base_ptr+0x04);
udelay(100);
writel_relaxed(0x080, base_ptr+0x04);
mb();
iounmap(base_ptr);
return 0;
}
static int __cpuinit msm8960_release_secondary(unsigned long base,
unsigned int cpu)
{
void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);
if (!base_ptr)
return -ENODEV;
msm_spm_turn_on_cpu_rail(MSM8960_SAW2_BASE_ADDR, cpu);
writel_relaxed(0x109, base_ptr+0x04);
writel_relaxed(0x101, base_ptr+0x04);
mb();
ndelay(300);
writel_relaxed(0x121, base_ptr+0x04);
mb();
udelay(2);
writel_relaxed(0x120, base_ptr+0x04);
mb();
udelay(2);
writel_relaxed(0x100, base_ptr+0x04);
mb();
udelay(100);
writel_relaxed(0x180, base_ptr+0x04);
mb();
iounmap(base_ptr);
return 0;
}
static int power_on_l2_msm8994(struct device_node *l2ccc_node, u32 pon_mask,
int cpu)
{
u32 pon_status;
void __iomem *l2_base;
int ret = 0;
uint32_t val;
struct device_node *vctl_node;
vctl_node = of_parse_phandle(l2ccc_node, "qcom,vctl-node", 0);
if (!vctl_node)
return -ENODEV;
l2_base = of_iomap_by_name(l2ccc_node, "l2-base");
if (!l2_base)
return -ENOMEM;
pon_status = (__raw_readl(l2_base + L2_PWR_CTL) & pon_mask) == pon_mask;
/* Check L2 SPM Status */
if (pon_status) {
ret = kick_l2spm(l2ccc_node, vctl_node);
iounmap(l2_base);
return ret;
}
/* Need to power on the rail */
ret = of_property_read_u32(l2ccc_node, "qcom,vctl-val", &val);
if (ret) {
iounmap(l2_base);
pr_err("Unable to read L2 voltage\n");
return -EFAULT;
}
ret = msm_spm_turn_on_cpu_rail(vctl_node, val, cpu, L2_VREG_CTL);
if (ret) {
iounmap(l2_base);
pr_err("Error turning on power rail.\n");
return -EFAULT;
}
/* Enable L1 invalidation by h/w */
writel_relaxed(0x00000000, l2_base + L1_RST_DIS);
mb();
/* Assert PRESETDBGn */
writel_relaxed(0x00400000 , l2_base + L2_PWR_CTL_OVERRIDE);
mb();
/* Close L2/SCU Logic GDHS and power up the cache */
writel_relaxed(0x00029716 , l2_base + L2_PWR_CTL);
mb();
udelay(8);
/* De-assert L2/SCU memory Clamp */
writel_relaxed(0x00023716 , l2_base + L2_PWR_CTL);
mb();
/* Wakeup L2/SCU RAMs by deasserting sleep signals */
writel_relaxed(0x0002371E , l2_base + L2_PWR_CTL);
mb();
udelay(8);
/* Un-gate clock and wait for sequential waking up
* of L2 rams with a delay of 2*X0 cycles
*/
writel_relaxed(0x0002371C , l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* De-assert L2/SCU logic clamp */
writel_relaxed(0x0002361C , l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* De-assert L2/SCU logic reset */
writel_relaxed(0x00022218 , l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* Turn on the PMIC_APC */
writel_relaxed(0x10022218 , l2_base + L2_PWR_CTL);
mb();
/* De-assert PRESETDBGn */
writel_relaxed(0x00000000 , l2_base + L2_PWR_CTL_OVERRIDE);
mb();
iounmap(l2_base);
return 0;
}
static int power_on_l2_msm8976(struct device_node *l2ccc_node, u32 pon_mask,
int cpu)
{
u32 pon_status;
void __iomem *l2_base;
int ret = 0;
struct device_node *vctl_node;
uint32_t val;
vctl_node = of_parse_phandle(l2ccc_node, "qcom,vctl-node", 0);
if (!vctl_node)
return -ENODEV;
l2_base = of_iomap_by_name(l2ccc_node, "l2-base");
if (!l2_base)
return -ENOMEM;
/* Skip power-on sequence if l2 cache is already powered up */
pon_status = (__raw_readl(l2_base + L2_PWR_CTL) & pon_mask)
== pon_mask;
/* Check L2 SPM Status */
if (pon_status) {
ret = kick_l2spm(l2ccc_node, vctl_node);
iounmap(l2_base);
return ret;
}
/* Need to power on the rail */
ret = of_property_read_u32(l2ccc_node, "qcom,vctl-val", &val);
if (ret) {
iounmap(l2_base);
pr_err("Unable to read L2 voltage\n");
return -EFAULT;
}
ret = msm_spm_turn_on_cpu_rail(vctl_node, val, cpu, L2_VREG_CTL);
if (ret) {
iounmap(l2_base);
pr_err("Error turning on power rail.\n");
return -EFAULT;
}
/* Close Few of the head-switches for L2SCU logic */
writel_relaxed(0x10F700, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* Close Rest of the head-switches for L2SCU logic */
writel_relaxed(0x410F700, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* Assert PRESETDBG */
writel_relaxed(0x400000, l2_base + L2_PWR_CTL_OVERRIDE);
mb();
udelay(2);
/* De-assert L2/SCU memory Clamp */
writel_relaxed(0x4103700, l2_base + L2_PWR_CTL);
/* Assert L2 memory slp_nret_n */
writel_relaxed(0x4103703, l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* Assert L2 memory slp_ret_n */
writel_relaxed(0x4101703, l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* Assert L2 memory wl_en_clk */
writel_relaxed(0x4101783, l2_base + L2_PWR_CTL);
mb();
udelay(1);
/* De-assert L2 memory wl_en_clk */
writel_relaxed(0x4101703, l2_base + L2_PWR_CTL);
mb();
/* Enable clocks via SW_CLK_EN */
writel_relaxed(0x01, l2_base + L2_CORE_CBCR);
/* De-assert L2/SCU logic clamp */
writel_relaxed(0x4101603, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* De-assert PRESETDBG */
writel_relaxed(0x0, l2_base + L2_PWR_CTL_OVERRIDE);
/* De-assert L2/SCU Logic reset */
writel_relaxed(0x4100203, l2_base + L2_PWR_CTL);
mb();
udelay(54);
/* Turn on the PMIC_APC */
writel_relaxed(0x14100203, l2_base + L2_PWR_CTL);
/* Set H/W clock control for the cluster CBC block */
writel_relaxed(0x03, l2_base + L2_CORE_CBCR);
mb();
iounmap(l2_base);
return 0;
}
