void set_kpd_pmic_mode()
{
unsigned int a,c;
a = pwrap_read(0x0502,&c);
if(a != 0)
printf("kpd write fail, addr: 0x0502\n");
printf("kpd read addr: 0x0502: data:0x%x\n", c);
c = c&0xFFFE;//0x4000;
a = pwrap_write(0x0502,c);
if(a != 0)
printf("kpd write fail, addr: 0x0502\n");
#ifdef MT65XX_PMIC_RST_KEY
pmic_config_interface(GPIO_SMT_CON3,0x01, PMIC_RG_HOMEKEY_PUEN_MASK, PMIC_RG_HOMEKEY_PUEN_SHIFT);//pull up homekey pin of PMIC for 89 project
#endif
mt65xx_reg_sync_writew(0x1, KP_PMIC);
printf("kpd register for pmic set!\n");
return;
}
void uart_setbrg()
{
unsigned int byte,speed;
unsigned int highspeed;
unsigned int quot, divisor, remainder;
unsigned int uartclk;
unsigned short data, high_speed_div, sample_count, sample_point;
unsigned int tmp_div;
speed = g_brg;
////FIXME Disable for MT6582 LK Porting
uartclk = UART_SRC_CLK;
//uartclk = (unsigned int)(mtk_get_bus_freq()*1000/4);
if (speed <= 115200 ) {
highspeed = 0;
quot = 16;
} else {
highspeed = 3;
quot = 1;
}
if (highspeed < 3) { /*0~2*/
/* Set divisor DLL and DLH */
divisor = uartclk / (quot * speed);
remainder = uartclk % (quot * speed);
if (remainder >= (quot / 2) * speed)
divisor += 1;
mt65xx_reg_sync_writew(highspeed, UART_HIGHSPEED(g_uart));
byte = DRV_Reg32(UART_LCR(g_uart)); /* DLAB start */
mt65xx_reg_sync_writel((byte | UART_LCR_DLAB), UART_LCR(g_uart));
mt65xx_reg_sync_writel((divisor & 0x00ff), UART_DLL(g_uart));
mt65xx_reg_sync_writel(((divisor >> 8)&0x00ff), UART_DLH(g_uart));
mt65xx_reg_sync_writel(byte, UART_LCR(g_uart)); /* DLAB end */
}
static int cyttsp4_init(struct cyttsp4_core_platform_data *pdata,
int on, struct device *dev)
{
printk("cyttsp4_init\n");
/* BEGIN PN: DTS2013031908354 ,Added by l00184147, 2013/3/19*/
//hw_product_type board_id;
//board_id=get_hardware_product_version();
/* END PN: DTS2013031908354 ,Added by l00184147, 2013/3/19*/
int rc = 0;
struct kobject *properties_kobj;
kal_uint16 temp;
int ret;
tpd_type_cap = 1;
tpd_load_status = 1;
/* BEGIN PN: DTS2013053100307 ,Modified by l00184147, 2013/05/31*/
/* BEGIN PN: DTS2013041600131 ,Modified by l00184147, 2013/4/16*/
/* BEGIN PN: DTS2013031908354 ,Modified by l00184147, 2013/3/19*/
if (on) {
cyttsp4_init_i2c_alloc_dma_buffer();
/* BEGIN PN: DTS2013060600352 ,Deleted by l00184147, 2013/06/06*/
//pull up reset pin after poweron the touch controller
/* END PN: DTS2013060600352 ,Deleted by l00184147, 2013/06/06*/
mt_set_gpio_mode(GPIO_CTP_EINT_PIN, GPIO_CTP_EINT_PIN_M_EINT);
mt_set_gpio_dir(GPIO_CTP_EINT_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_enable(GPIO_CTP_EINT_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_CTP_EINT_PIN, GPIO_PULL_UP);
temp = DRV_Reg(0xF0005920);
temp |= (0x04);
mt65xx_reg_sync_writew(temp, 0xF0005920);
if(1/*(board_id & HW_VER_MAIN_MASK) == HW_G750_VER*/)
{
#ifdef HW_HAVE_TP_THREAD //for HUAWEI
//increasing VGP2 to 1.85, please help to measure it from HW
hwPowerOn(MT6323_POWER_LDO_VGP1, VOL_2800, "TP");
hwPowerOn(MT6323_POWER_LDO_VGP3, VOL_1800, "TP");
//pmic_config_interface(0x0534, 0xd, 0xf, 8); //+60mV
pmic_config_interface(0x0534, 0xb, 0xf, 8); //+100mV
#else
//TODO
#endif
properties_kobj = kobject_create_and_add("board_properties", NULL);
if (properties_kobj)
ret = sysfs_create_group(properties_kobj,
&cyttsp4_properties_attr_group);
if (!properties_kobj || ret)
pr_err("%s: failed to create board_properties\n", __func__);
}
else
pr_err("power on cyttsp4 error\n");
/* BEGIN PN: DTS2013060600352 ,Added by l00184147, 2013/06/06*/
//pull up reset pin after poweron the touch controller
mt_set_gpio_mode(GPIO_CTP_RST_PIN, GPIO_CTP_RST_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_CTP_RST_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_CTP_RST_PIN, GPIO_OUT_ONE);
/* END PN: DTS2013060600352 ,Added by l00184147, 2013/06/06*/
}
else {
if(1/*(board_id & HW_VER_MAIN_MASK) == HW_G750_VER*/)
{
hwPowerDown(MT6323_POWER_LDO_VGP1, "TP");
hwPowerDown(MT6323_POWER_LDO_VGP2, "TP");
}
else
pr_err("power down cyttsp4 error\n");
cyttsp4_init_i2c_free_dma_buffer();
}
/* END PN: DTS2013031908354 ,Modified by l00184147, 2013/3/19*/
/* END PN: DTS2013041600131 ,Modified by l00184147, 2013/4/16*/
/* END PN: DTS2013053100307 ,Modified by l00184147, 2013/05/31*/
return rc;
}
static void internal_md_power_down(void)
{
/**
* MDMCU Control Power Registers
*/
#define MD_TOPSM_BASE (0x20030000)
#define MD_TOPSM_RM_TMR_PWR0(base) ((volatile unsigned int*)((base) + 0x0018))
#define MD_TOPSM_SM_REQ_MASK(base) ((volatile unsigned int*)((base) + 0x08B0))
#define MD_TOPSM_RM_PWR_CON0(base) ((volatile unsigned int*)((base) + 0x0800))
#define MD_TOPSM_RM_PWR_CON1(base) ((volatile unsigned int*)((base) + 0x0804))
#define MD_TOPSM_RM_PLL_MASK0(base) ((volatile unsigned int*)((base) + 0x0830))
#define MD_TOPSM_RM_PLL_MASK1(base) ((volatile unsigned int*)((base) + 0x0834))
#define MODEM2G_TOPSM_BASE (0x23010000)
#define MODEM2G_TOPSM_RM_CLK_SETTLE(base) ((volatile unsigned int*)((base) + 0x0000))
#define MODEM2G_TOPSM_RM_TMRPWR_SETTLE(base) ((volatile unsigned int*)((base) + 0x0004))
#define MODEM2G_TOPSM_RM_TMR_TRG0(base) ((volatile unsigned int*)((base) + 0x0010))
#define MODEM2G_TOPSM_RM_TMR_TRG1(base) ((volatile unsigned int*)((base) + 0x0014))
#define MODEM2G_TOPSM_RM_TMR_PWR0(base) ((volatile unsigned int*)((base) + 0x0018))
#define MODEM2G_TOPSM_RM_TMR_PWR1(base) ((volatile unsigned int*)((base) + 0x001C))
#define MODEM2G_TOPSM_RM_PWR_CON0(base) ((volatile unsigned int*)((base) + 0x0800))
#define MODEM2G_TOPSM_RM_PWR_CON1(base) ((volatile unsigned int*)((base) + 0x0804))
#define MODEM2G_TOPSM_RM_PWR_CON2(base) ((volatile unsigned int*)((base) + 0x0808))
#define MODEM2G_TOPSM_RM_PWR_CON3(base) ((volatile unsigned int*)((base) + 0x080C))
#define MODEM2G_TOPSM_RM_PWR_CON4(base) ((volatile unsigned int*)((base) + 0x0810))
#define MODEM2G_TOPSM_RM_PWR_CON5(base) ((volatile unsigned int*)((base) + 0x0814))
#define MODEM2G_TOPSM_RM_PWR_CON6(base) ((volatile unsigned int*)((base) + 0x0818))
#define MODEM2G_TOPSM_RM_PWR_CON7(base) ((volatile unsigned int*)((base) + 0x081C))
#define MODEM2G_TOPSM_RM_PLL_MASK0(base) ((volatile unsigned int*)((base) + 0x0830))
#define MODEM2G_TOPSM_RM_PLL_MASK1(base) ((volatile unsigned int*)((base) + 0x0834))
#define MODEM2G_TOPSM_RM_PLL_MASK2(base) ((volatile unsigned int*)((base) + 0x0838))
#define MODEM2G_TOPSM_RM_PLL_MASK3(base) ((volatile unsigned int*)((base) + 0x083C))
#define MODEM2G_TOPSM_SM_REQ_MASK(base) ((volatile unsigned int*)((base) + 0x08B0))
/**
*[TDD] MDMCU Control Power Registers
*/
#define TDD_BASE (0x24000000)
#define TDD_HALT_CFG_ADDR(base) ((volatile unsigned int*)((base) + 0x0000))
#define TDD_HALT_STATUS_ADDR(base) ((volatile unsigned int*)((base) + 0x0002))
unsigned short status;
unsigned short i;
unsigned int md_topsm_base, modem2g_topsm_base, tdd_base;
printk("[ccci/ctl] (0)internal md disabled, so power down!\n");
//printk("[ccci/ctl] (0)call md_power_on...\n");
md_power_on(0);
md_topsm_base = (unsigned int)ioremap_nocache(MD_TOPSM_BASE, 0x840);
modem2g_topsm_base = (unsigned int)ioremap_nocache(MODEM2G_TOPSM_BASE, 0x8C0);
tdd_base = (unsigned int)ioremap_nocache(TDD_BASE, 0x010);
//printk("[ccci/ctl] (0)MD2G/HSPA power down...\n");
/*[MD2G/HSPA] MDMCU Control Power Down Sequence*/
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON0(modem2g_topsm_base)) | 0x44, MODEM2G_TOPSM_RM_PWR_CON0(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON1(modem2g_topsm_base)) | 0x44, MODEM2G_TOPSM_RM_PWR_CON1(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON2(modem2g_topsm_base)) | 0x44, MODEM2G_TOPSM_RM_PWR_CON2(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON3(modem2g_topsm_base)) | 0x44, MODEM2G_TOPSM_RM_PWR_CON3(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON4(modem2g_topsm_base)) | 0x44, MODEM2G_TOPSM_RM_PWR_CON4(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON0(modem2g_topsm_base)) & 0xFFFFFF7F, MODEM2G_TOPSM_RM_PWR_CON0(modem2g_topsm_base));
mt65xx_reg_sync_writel(0x00000200, MODEM2G_TOPSM_RM_PWR_CON0(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON1(modem2g_topsm_base)) & 0xFFFFFF7F, MODEM2G_TOPSM_RM_PWR_CON1(modem2g_topsm_base));
mt65xx_reg_sync_writel(0x00000200, MODEM2G_TOPSM_RM_PWR_CON1(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON2(modem2g_topsm_base)) & 0xFFFFFF7F, MODEM2G_TOPSM_RM_PWR_CON2(modem2g_topsm_base));
mt65xx_reg_sync_writel(0x00000200, MODEM2G_TOPSM_RM_PWR_CON2(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON3(modem2g_topsm_base)) & 0xFFFFFF7F, MODEM2G_TOPSM_RM_PWR_CON3(modem2g_topsm_base));
mt65xx_reg_sync_writel(0x00000200, MODEM2G_TOPSM_RM_PWR_CON3(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON4(modem2g_topsm_base)) & 0xFFFFFF7F, MODEM2G_TOPSM_RM_PWR_CON4(modem2g_topsm_base));
mt65xx_reg_sync_writel(0x00000200, MODEM2G_TOPSM_RM_PWR_CON4(modem2g_topsm_base));
mt65xx_reg_sync_writel(0xFFFFFFFF, MD_TOPSM_SM_REQ_MASK(md_topsm_base));
mt65xx_reg_sync_writel(0x00000000, MODEM2G_TOPSM_RM_TMR_PWR0(modem2g_topsm_base));
mt65xx_reg_sync_writel(0x00000000, MODEM2G_TOPSM_RM_TMR_PWR1(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON0(modem2g_topsm_base)) & ~(0x1<<2) & ~(0x1<<6), MODEM2G_TOPSM_RM_PWR_CON0(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON1(modem2g_topsm_base)) & ~(0x1<<2) & ~(0x1<<6), MODEM2G_TOPSM_RM_PWR_CON1(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON2(modem2g_topsm_base)) & ~(0x1<<2) & ~(0x1<<6), MODEM2G_TOPSM_RM_PWR_CON2(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON3(modem2g_topsm_base)) & ~(0x1<<2) & ~(0x1<<6), MODEM2G_TOPSM_RM_PWR_CON3(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PWR_CON4(modem2g_topsm_base)) & ~(0x1<<2) & ~(0x1<<6), MODEM2G_TOPSM_RM_PWR_CON4(modem2g_topsm_base));
//printk("[ccci/ctl] (0)TDD power down...\n");
/*[TDD] MDMCU Control Power Down Sequence*/
mt65xx_reg_sync_writew(0x1, TDD_HALT_CFG_ADDR(tdd_base));
status = *((volatile unsigned short*)TDD_HALT_CFG_ADDR(tdd_base));
while ((status & 0x1) == 0) {
if (status & 0x1) { //halted
/*TINFO=''TDD is in *HALT* STATE*/
} else if (status & 0x2) { //normal
/*TINFO=''TDD is in *NORMAL* STATE*/
} else if (status & 0x4) { //sleep
/*TINFO=''TDD is in *SLEEP* STATE*/
}
i = 100;
while(i--);
status = *((volatile unsigned short*)TDD_HALT_CFG_ADDR(tdd_base));
}
//printk("[ccci/ctl] (0)ABB power down...\n");
/*[ABB] MDMCU Control Power Down Sequence*/
mt65xx_reg_sync_writel((*MD_TOPSM_RM_PWR_CON0(md_topsm_base)) | 0x00000090, MD_TOPSM_RM_PWR_CON0(md_topsm_base));
mt65xx_reg_sync_writel((*MD_TOPSM_RM_PLL_MASK0(md_topsm_base)) | 0xFFFF0000, MD_TOPSM_RM_PLL_MASK0(md_topsm_base));
mt65xx_reg_sync_writel((*MD_TOPSM_RM_PLL_MASK1(md_topsm_base)) | 0x000000FF, MD_TOPSM_RM_PLL_MASK1(md_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PLL_MASK0(modem2g_topsm_base)) | 0xFFFFFFFF, MODEM2G_TOPSM_RM_PLL_MASK0(modem2g_topsm_base));
mt65xx_reg_sync_writel((*MODEM2G_TOPSM_RM_PLL_MASK1(modem2g_topsm_base)) | 0x0000000F, MODEM2G_TOPSM_RM_PLL_MASK1(modem2g_topsm_base));
//printk("[ccci/ctl] (0)MDMCU power down...\n");
/*[MDMCU] APMCU Control Power Down Sequence*/
mt65xx_reg_sync_writel(0xFFFFFFFF, MD_TOPSM_SM_REQ_MASK(md_topsm_base));
mt65xx_reg_sync_writel(0x00000000, MD_TOPSM_RM_TMR_PWR0(md_topsm_base));
mt65xx_reg_sync_writel(0x0005229A, MD_TOPSM_RM_PWR_CON0(md_topsm_base));
mt65xx_reg_sync_writel(0xFFFFFFFF, MD_TOPSM_RM_PLL_MASK0(md_topsm_base));
mt65xx_reg_sync_writel(0xFFFFFFFF, MD_TOPSM_RM_PLL_MASK1(md_topsm_base));
mt65xx_reg_sync_writel(0xFFFFFFFF, MODEM2G_TOPSM_SM_REQ_MASK(modem2g_topsm_base));
mt65xx_reg_sync_writel(0xFFFFFFFF, MODEM2G_TOPSM_RM_PLL_MASK0(modem2g_topsm_base));
mt65xx_reg_sync_writel(0xFFFFFFFF, MODEM2G_TOPSM_RM_PLL_MASK1(modem2g_topsm_base));
//printk("[ccci/ctl] (0)call md_power_off...\n");
md_power_off(0, 100);
iounmap((void*)md_topsm_base);
iounmap((void*)modem2g_topsm_base);
iounmap((void*)tdd_base);
}
