/* * Initialization, must be called once on start up, may be called * repeatedly to change the speed and slave addresses. */ void i2c_init(int speed, int slaveaddr) { MV_TWSI_ADDR slave; slave.type = ADDR7_BIT; slave.address = slaveaddr; mvTwsiInit(i2c_current_bus, speed, CONFIG_SYS_TCLK, &slave, 0); }
int board_init (void) { DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FLASH_CFI_DRIVER int portwidth; MV_U32 devParam; #endif #if defined(MV_INCLUDE_TWSI) MV_TWSI_ADDR slave; #endif MV_GPP_HAL_DATA gppHalData; unsigned int i; maskAllInt(); /* must initialize the int in order for udelay to work */ //alior interrupt_init(); timer_init(); /* Init the Board environment module (device bank params init) */ mvBoardEnvInit(); #if defined(MV_INCLUDE_TWSI) slave.type = ADDR7_BIT; slave.address = 0; mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); #endif /* Init the Controlloer environment module (MPP init) */ mvCtrlEnvInit(); mvBoardDebugLed(3); /* Init the Controller CPU interface */ mvCpuIfInit(mvCpuAddrWinMap); /* Init the GPIO sub-system */ gppHalData.ctrlRev = mvCtrlRevGet(); mvGppInit(&gppHalData); /* arch number of Integrator Board */ gd->bd->bi_arch_number = 529; //KW2 arch number /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; /* relocate the exception vectors */ /* U-Boot is running from DRAM at this stage */ for(i = 0; i < 0x100; i+=4) { *(unsigned int *)(0x0 + i) = *(unsigned int*)(TEXT_BASE + i); } mvBoardDebugLed(4); return 0; }
int board_init(void) { DECLARE_GLOBAL_DATA_PTR; if (whoAmI() != 0) return 0; #if defined(MV_INCLUDE_TWSI) MV_TWSI_ADDR slave; #endif unsigned int i; maskAllInt(); /* Init the Board environment module (device bank params init) */ mvBoardEnvInit(); #if defined(MV_INCLUDE_TWSI) slave.type = ADDR7_BIT; slave.address = 0; mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); #endif /* Init the Controlloer environment module (MPP init) */ mvCtrlEnvInit(); #if defined(CONFIG_DISPLAY_CPUINFO) late_print_cpuinfo(); /* display cpu info (and speed) */ #endif mvBoardDebugLed(2); mvCpuIfInit(mvCpuAddrWinMap); #ifdef MV_NOR_BOOT env_init(); #endif /* Init the GPIO sub-system */ MV_GPP_HAL_DATA gppHalData; gppHalData.ctrlRev = mvCtrlRevGet(); mvGppInit(&gppHalData); gd->bd->bi_arch_number = 528; gd->bd->bi_boot_params = 0x00000100; /* relocate the exception vectors */ /* U-Boot is running from DRAM at this stage */ for (i = 0; i < 0x100; i += 4) *(unsigned int*)(0x0 + i) = *(unsigned int*)(CONFIG_SYS_TEXT_BASE + i); mvBoardDebugLed(4); return 0; }
/* u-boot interface function to SDRAM init - this is where all the * controlling logic happens */ long int initdram(int board_type) { MV_VOIDFUNCPTR pRom; MV_U32 forcedCl; /* Forced CAS Latency */ MV_U32 totalSize; char * env; MV_TWSI_ADDR slave; /* r0 <- current position of code */ /* test if we run from flash or RAM */ if(dramBoot != 1) { slave.type = ADDR7_BIT; slave.address = 0; mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); /* Calculating MIN/MAX CAS latency according to user settings */ env = getenv("CASset"); if(env && (strcmp(env,"1.5") == 0)) { forcedCl = 15; } else if(env && (strcmp(env,"2") == 0)) { forcedCl = 20; } else if(env && (strcmp(env,"2.5") == 0)) { forcedCl = 25; } else if(env && (strcmp(env,"3") == 0)) { forcedCl = 30; } else if(env && (strcmp(env,"4") == 0)) { forcedCl = 40; } else if(env && (strcmp(env,"5") == 0)) { forcedCl = 50; } else if(env && (strcmp(env,"6") == 0)) { forcedCl = 60; } else { forcedCl = 0; } /* detect the dram configuartion parameters */ if (MV_OK != mvDramIfDetect(forcedCl,1)) { printf("DRAM Auto Detection Failed! System Halt!\n"); return 0; } /* set the dram configuration */ /* Calculate jump address of _mvDramIfConfig() */ #if defined(MV_BOOTROM) pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + (MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE + (MV_VOIDFUNCPTR)MONITOR_HEADER_LEN); #else pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + (MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE); #endif (*pRom) (); /* Jump to _mvDramIfConfig*/ } totalSize = mvDramIfSizeGet(); return(totalSize); }
int board_init (void) { DECLARE_GLOBAL_DATA_PTR; int clock_divisor; unsigned int i; MV_GPP_HAL_DATA gppHalData; clock_divisor = (CONFIG_SYS_TCLK / 16)/115200; /* muti-core support, initiate each Uart to each cpu */ mvUartInit(whoAmI(), clock_divisor, mvUartBase(whoAmI())); if (whoAmI() != 0) return 0; #if defined(MV_INCLUDE_TWSI) MV_TWSI_ADDR slave; #endif maskAllInt(); /* must initialize the int in order for udelay to work */ /* interrupt_init(); - no interrupt handling in u-boot */ timer_init(); /* Init the Board environment module (device bank params init) */ mvBoardEnvInit(); #if defined(MV_INCLUDE_TWSI) slave.type = ADDR7_BIT; slave.address = 0; mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0); #endif /* Init the Controlloer environment module (MPP init) */ mvCtrlEnvInit(); #if defined(CONFIG_DISPLAY_CPUINFO) late_print_cpuinfo(); /* display cpu info (and speed) */ #endif mvBoardDebugLed(2); /* Init the Controller CPU interface */ mvCpuIfInit(mvCpuAddrWinMap); #if defined(MV_NOR_BOOT) env_init(); #endif if (mvBoardCpssBoardIdSet(mvBoardIdGet()) != MV_OK) printf("%s: Error: Failed to set Board ID for CPSS!\n", __func__); /* Init the GPIO sub-system */ gppHalData.ctrlRev = mvCtrlRevGet(); mvGppInit(&gppHalData); /* arch number of Integrator Board */ gd->bd->bi_arch_number=mv_get_arch_number(); /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; /* relocate the exception vectors */ /* U-Boot is running from DRAM at this stage */ for(i = 0; i < 0x100; i+=4) { *(unsigned int *)(0x0 + i) = *(unsigned int*)(CONFIG_SYS_TEXT_BASE + i); } mvBoardDebugLed(4); return 0; }
/******************************************************************************* * mvCtrlHighSpeedSerdesPhyConfig * * DESCRIPTION: This is the main function which configure the * PU sequence of the ser-des * * INPUT: * None. * * OUTPUT: * None. * * RETURN: * MV_OK - success * MV_ERROR - failure *******************************************************************************/ MV_STATUS mvCtrlHighSpeedSerdesPhyConfig(MV_VOID) { MV_U32 serdesLaneNum, pexUnit; MV_U32 uiReg; MV_BIN_SERDES_UNIT_INDX serdesLaneCfg; MV_U32 regAddr[16][11], regVal[16][11]; /* addr/value for each line @ every setup step */ MV_U8 maxSerdesLanes; MV_U32 tmp; MV_U32 tempReg, tempPexReg; MV_U32 pexIf=0; MV_U32 first_busno, next_busno; MV_U32 addr; MV_TWSI_ADDR slave; MV_U32 boardId = mvBoardIdIndexGet(mvBoardIdGet()); maxSerdesLanes = mvCtrlSerdesMaxLanesGet(); if (maxSerdesLanes == 0) return MV_OK; /*Set MPP1 for twsi access */ uiReg = (MV_REG_READ(MPP_CONTROL_REG(1)) & 0x00FFFFFF) | 0x22000000; MV_REG_WRITE(MPP_CONTROL_REG(1), uiReg); /* TWSI init */ slave.type = ADDR7_BIT; slave.address = 0; mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); mvUartInit(); /* update board configuration (serdes lane topology and speed), if needed */ mvBoardUpdateBoardTopologyConfig(boardId); /* Initialize board configuration database */ boardLaneConfig[0] = SERDES_UNIT_PEX; /* SerDes 0 is alwyas PCIe0*/ boardLaneConfig[1] = boardTopologyConfig[boardId].serdesTopology.lane1; boardLaneConfig[2] = boardTopologyConfig[boardId].serdesTopology.lane2; boardLaneConfig[3] = boardTopologyConfig[boardId].serdesTopology.lane3; memset(regAddr, 0, sizeof(regAddr)); memset(regVal, 0, sizeof(regVal)); /* Check if DRAM is already initialized */ if (MV_REG_READ(REG_BOOTROM_ROUTINE_ADDR) & (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { DEBUG_INIT_S("High speed PHY - Version: "); DEBUG_INIT_S(SERDES_VERION); DEBUG_INIT_S(" - 2nd boot - Skip \n"); return MV_OK; } DEBUG_INIT_S("High speed PHY - Version: "); DEBUG_INIT_S(SERDES_VERION); DEBUG_INIT_S(" (COM-PHY-V20) \n"); DEBUG_INIT_FULL_C("SERDES 0=",boardLaneConfig[0],2); DEBUG_INIT_FULL_C("SERDES 1=",boardLaneConfig[1],2); DEBUG_INIT_FULL_C("SERDES 2=",boardLaneConfig[2],2); DEBUG_INIT_FULL_C("SERDES 3=",boardLaneConfig[3],2); /*------------------------------------------*/ /* STEP - 1.5 Power Down PLL, RX, TX all phys */ /*------------------------------------------*/ for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) { uiReg=MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum)); uiReg &= ~PIN_TX_IDLE_MASK; uiReg &= ~(PHY_POWER_UP_PLL_MASK | PHY_POWER_UP_RX_MASK | PHY_POWER_UP_TX_MASK); MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg); } mvOsUDelay(10000); /*--------------------------------------------------------*/ /* STEP - 2 Reset PHY and PIPE (Zx: Un-reset, Ax: Reset)*/ /*--------------------------------------------------------*/ for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) { #ifndef CONFIG_ALP_A375_ZX_REV resetPhyAndPipe(serdesLaneNum, MV_TRUE); #else resetPhyAndPipe(serdesLaneNum, MV_FALSE); #endif } /*--------------------------------*/ /* STEP - 2 Common PHYs Selectors */ /*--------------------------------*/ MV_REG_WRITE(COMMON_PHY_SELECTOR_REG, GetLaneSelectorConfig()); /*--------------------------------*/ /* STEP - 3 Configuration 1 */ /*--------------------------------*/ for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) { serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum); if(serdesLaneCfg >= SERDES_LAST_UNIT){ return MV_ERROR; } uiReg = MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum)); switch(serdesLaneCfg){ case SERDES_UNIT_USB3: #ifndef CONFIG_ALP_A375_ZX_REV A375_A0_COMMON_PHY_CONFIG(uiReg); #endif uiReg |= PHY_MODE_MASK; /* PHY Mode = USB */ uiReg |= PIPE_SELECT_MASK ; /* Select USB3_PEX */ break; case SERDES_UNIT_PEX: uiReg |= PIPE_SELECT_MASK ; /* Select USB3_PEX */ #ifndef CONFIG_ALP_A375_ZX_REV uiReg &= ~(PHY_MODE_MASK); /* PHY Mode = PEX */ A375_A0_COMMON_PHY_CONFIG(uiReg); #endif break; case SERDES_UNIT_SGMII: case SERDES_UNIT_SATA: #ifndef CONFIG_ALP_A375_ZX_REV A375_A0_COMMON_PHY_CONFIG(uiReg); #endif uiReg &= ~(PIPE_SELECT_MASK); /* Select SATA_SGMII */ uiReg |= POWER_UP_IVREF_MASK; /* Power UP IVREF = Power Up */ break; case SERDES_UNIT_UNCONNECTED: default: break; } /* Serdes speed config */ tmp = getSerdesSpeedConfig(boardId, serdesLaneCfg); uiReg &= ~(GEN_RX_MASK); /* SERDES RX Speed config */ uiReg |= tmp<<GEN_RX_OFFS; uiReg &= ~(GEN_TX_MASK); /* SERDES TX Speed config */ uiReg |= tmp<<GEN_TX_OFFS; MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg); } #ifndef CONFIG_ALP_A375_ZX_REV /*------------------------------------------*/ /* STEP - 3.5 Unreset PHY and PIPE(only Ax)*/ /*------------------------------------------*/ for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) { resetPhyAndPipe(serdesLaneNum, MV_FALSE); } #endif /*----------------------------------------*/ /* STEP - 4 COMPHY register configuration */ /*----------------------------------------*/ for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) { serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum); if(serdesLaneCfg >= SERDES_LAST_UNIT){ return MV_ERROR; } switch(serdesLaneCfg){ case SERDES_UNIT_PEX: MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x25); /* Enable soft_reset*/ MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC60); /* PHY Mode = PEX */ #ifndef CONFIG_ALP_A375_ZX_REV MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6017); /* REFCLK SEL =0x0 (100Mhz) */ MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */ MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */ A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum); #else MV_REG_WRITE(KVCO_CALOBRATION_CONTROL_REG(serdesLaneNum),0x40); /* use_max_pll_rate=0x0, ext_force_cal_done=0x0 */ #endif MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x24); /* Release soft_reset */ break; case SERDES_UNIT_USB3: MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x21); /* Enable soft_reset*/ MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFCA0); /* PHY Mode = USB3 */ #ifndef CONFIG_ALP_A375_ZX_REV MV_REG_WRITE(LANE_CONFIGURATION_4_REG(serdesLaneNum),0x13); /* Ref_Clk =100Mhz */ MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6017); /* REFCLK SEL =0x0 (100Mhz) */ MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */ MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */ A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum); #else MV_REG_WRITE(KVCO_CALOBRATION_CONTROL_REG(serdesLaneNum),0x40); /* use_max_pll_rate=0x0, ext_force_cal_done=0x0 */ MV_REG_WRITE(GENERETION_2_SETTINGS_1_REG(serdesLaneNum),0x149); /* Mulitiple frequency setup */ #endif MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x20); /* Release soft_reset */ break; case SERDES_UNIT_SATA: MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC01); /* PHY Mode = SATA */ MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6417); /* REFCLK SEL =0x1 (25Mhz) */ #ifndef CONFIG_ALP_A375_ZX_REV MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */ MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */ MV_REG_WRITE(DIGITAL_RESERVED0_REG(serdesLaneNum),0xE); /* Reg_sq_de_glitch_en */ A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum); #else MV_REG_WRITE(RESERVED_46_REG(serdesLaneNum),0xFF00); #endif break; case SERDES_UNIT_SGMII: MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC81); /* PHY Mode = SGMII */ /*moti need to change offset*/ MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x0); /* SEL_BITS = 0x0 (10-bits mode) */ MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6417); /* REFCLK SEL =0x1 (25Mhz) */ #ifndef CONFIG_ALP_A375_ZX_REV MV_REG_WRITE(DIGITAL_RESERVED0_REG(serdesLaneNum),0xE); /* Reg_sq_de_glitch_en */ A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum); #else MV_REG_WRITE(RESERVED_46_REG(serdesLaneNum),0xFF00); /* Enable soft_reset*/ #endif MV_REG_WRITE(PHY_ISOLATION_MODE_CONTROL_REG(serdesLaneNum),0x166); /* Set PHY_GEN_TX/RX to 1.25Gbps */ break; case SERDES_UNIT_UNCONNECTED: default: break; } } /*------------------------------------------*/ /* STEP - 4.5 Power up PLL, RX, TX all phys */ /*------------------------------------------*/ for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) { uiReg=MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum)); uiReg |= (PHY_POWER_UP_PLL_MASK | PHY_POWER_UP_RX_MASK | PHY_POWER_UP_TX_MASK); MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg); } #ifndef CONFIG_ALP_A375_ZX_REV mvOsUDelay(5000); /*--------------------------------------------------------------------*/ /* STEP - 4.6 (Only SGMII/SATA): WAIT for PHY Power up sequence to finish */ /*--------------------------------------------------------------------*/ for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) { serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum); if(serdesLaneCfg >= SERDES_LAST_UNIT){ return MV_ERROR; } switch(serdesLaneCfg){ case SERDES_UNIT_SATA: case SERDES_UNIT_SGMII: uiReg = MV_REG_READ(COMMON_PHY_STATUS1_REG(serdesLaneNum)); if ((uiReg & 0x6) != 0x6) { DEBUG_INIT_S("Phy Power up did't finished\n"); return MV_ERROR; } case SERDES_UNIT_UNCONNECTED: default: break; } } #endif /*----------------------------------------*/ /* STEP - 5 PEX Only */ /*----------------------------------------*/ for (pexUnit = 0; pexUnit < 4; pexUnit++) { if (boardLaneConfig[pexUnit] != SERDES_UNIT_PEX) continue; tmp = MV_REG_READ(PEX_CAPABILITIES_REG(pexUnit)); DEBUG_RD_REG(PEX_CAPABILITIES_REG(pexUnit), tmp ); tmp &= ~(0xf<<20); tmp |= (0x4<<20); MV_REG_WRITE(PEX_CAPABILITIES_REG(pexUnit),tmp); DEBUG_WR_REG(PEX_CAPABILITIES_REG(pexUnit),tmp); } tmp = MV_REG_READ(SOC_CTRL_REG); DEBUG_RD_REG(SOC_CTRL_REG, tmp); tmp &= ~(0x03); tmp |= 0x1<<PCIE0_ENABLE_OFFS; if (boardLaneConfig[1] == SERDES_UNIT_PEX) tmp |= 0x1<<PCIE1_ENABLE_OFFS; MV_REG_WRITE(SOC_CTRL_REG, tmp); DEBUG_WR_REG(SOC_CTRL_REG, tmp); /*----------------------------------------*/ /* STEP - 6 PEX Only - support gen1/gen2 */ /*----------------------------------------*/ next_busno = 0; mvOsDelay(150); for (pexIf = 0; pexIf < 2; pexIf++) // only pexIf 0 on { if (boardLaneConfig[pexIf] != SERDES_UNIT_PEX) continue; tmp = MV_REG_READ(PEX_DBG_STATUS_REG(pexIf)); DEBUG_RD_REG(PEX_DBG_STATUS_REG(pexIf), tmp); first_busno = next_busno; if ((tmp & 0x7f) == 0x7E) { next_busno++; tempPexReg = MV_REG_READ((PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CAPABILITY_REG))); DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CAPABILITY_REG)),tempPexReg ); tempPexReg &= (0xF); if (tempPexReg == 0x2) { tempReg = (MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) & 0xF0000) >> 16; DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG),tempReg ); /* check if the link established is GEN1 */ if (tempReg == 0x1) { mvPexLocalBusNumSet(pexIf, first_busno); mvPexLocalDevNumSet(pexIf, 1); DEBUG_INIT_FULL_S("PEX: pexIf "); DEBUG_INIT_FULL_D(pexIf, 1); DEBUG_INIT_FULL_S(", link is Gen1, checking the EP capability \n"); /* link is Gen1, check the EP capability */ addr = mvPexConfigRead(pexIf, first_busno, 0, 0, 0x34) & 0xFF; DEBUG_INIT_FULL_C("mvPexConfigRead: return addr=0x%x", addr,4); if (addr == 0xff) { DEBUG_INIT_FULL_C("mvPexConfigRead: return 0xff -->PEX (%d): Detected No Link.", pexIf,1); continue; } while ((mvPexConfigRead(pexIf, first_busno, 0, 0, addr) & 0xFF) != 0x10) { addr = (mvPexConfigRead(pexIf, first_busno, 0, 0, addr) & 0xFF00) >> 8; } if ((mvPexConfigRead(pexIf, first_busno, 0, 0, addr + 0xC) & 0xF) >= 0x2) { tmp = MV_REG_READ(PEX_LINK_CTRL_STATUS2_REG(pexIf)); DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp ); tmp &=~(BIT0 | BIT1); tmp |= BIT1; MV_REG_WRITE(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp); DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp); tmp = MV_REG_READ(PEX_CTRL_REG(pexIf)); DEBUG_RD_REG(PEX_CTRL_REG(pexIf), tmp ); tmp |= BIT10; MV_REG_WRITE(PEX_CTRL_REG(pexIf),tmp); DEBUG_WR_REG(PEX_CTRL_REG(pexIf),tmp); mvOsUDelay(10000);/* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state*/ DEBUG_INIT_FULL_S("PEX: pexIf "); DEBUG_INIT_FULL_D(pexIf, 1); DEBUG_INIT_FULL_S(", Link upgraded to Gen2 based on client cpabilities \n"); } else { DEBUG_INIT_FULL_S("PEX: pexIf "); DEBUG_INIT_FULL_D(pexIf, 1); DEBUG_INIT_FULL_S(", remains Gen1\n"); } } }
/******************************************************************************* * boardEepromGet - Get board identification from the EEPROM * * DESCRIPTION: * * INPUT: * * OUTPUT: * None. * * RETURN: * *******************************************************************************/ MV_STATUS boardEepromGet(BOARD_DATA *boardData) { MV_TWSI_SLAVE twsiSlave; MV_TWSI_ADDR slave; MV_U32 tclk; tclk = mvBoardTclkGet(); /* Init TWSI first */ slave.type = ADDR7_BIT; slave.address = 0x0; mvTwsiInit(100000, tclk, &slave, 0); twsiSlave.slaveAddr.address = MV_BOARD_ID_EEPROM; twsiSlave.slaveAddr.type = ADDR7_BIT; twsiSlave.validOffset = MV_TRUE; twsiSlave.offset = MV_BOARD_ID_EEPROM_OFFSET0; twsiSlave.moreThen256 = MV_FALSE; if(MV_OK != mvTwsiRead (&twsiSlave, (MV_U8*)boardData, sizeof(BOARD_DATA))) { /*mvOsOutput("Fail to read Board EEPROM from offset0");*/ return MV_FAIL; } #if defined(MV_CPU_LE) boardData->magic = MV_BYTE_SWAP_32BIT(boardData->magic); boardData->boardId = MV_BYTE_SWAP_16BIT(boardData->boardId); boardData->reserved1 = MV_BYTE_SWAP_32BIT(boardData->reserved1); boardData->reserved2 = MV_BYTE_SWAP_32BIT(boardData->reserved2); #endif if(boardData->magic == MV_BOARD_I2C_MAGIC) { return MV_OK; } twsiSlave.offset = MV_BOARD_ID_EEPROM_OFFSET1; twsiSlave.moreThen256 = MV_TRUE; if(MV_OK != mvTwsiRead (&twsiSlave, (MV_U8*)boardData, sizeof(BOARD_DATA))) { /*mvOsOutput("Fail to read Board EEPROM from offset1");*/ return MV_FAIL; } #if defined(MV_CPU_LE) boardData->magic = MV_BYTE_SWAP_32BIT(boardData->magic); boardData->boardId = MV_BYTE_SWAP_16BIT(boardData->boardId); boardData->reserved1 = MV_BYTE_SWAP_32BIT(boardData->reserved1); boardData->reserved2 = MV_BYTE_SWAP_32BIT(boardData->reserved2); #endif if(boardData->magic == MV_BOARD_I2C_MAGIC) { return MV_OK; } return MV_FAIL; }