static int ahci_mvebu_probe(struct platform_device *pdev) { struct ahci_host_priv *hpriv; const struct mbus_dram_target_info *dram; int rc; hpriv = ahci_platform_get_resources(pdev); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); rc = ahci_platform_enable_resources(hpriv); if (rc) return rc; dram = mv_mbus_dram_info(); if (!dram) return -ENODEV; ahci_mvebu_mbus_config(hpriv, dram); ahci_mvebu_regret_option(hpriv); rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info, 0, 0, 0); if (rc) goto disable_resources; return 0; disable_resources: ahci_platform_disable_resources(hpriv); return rc; }
int xhci_mvebu_mbus_init_quirk(struct platform_device *pdev) { struct resource *res; void __iomem *base; const struct mbus_dram_target_info *dram; res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!res) return -ENODEV; /* * We don't use devm_ioremap() because this mapping should * only exists for the duration of this probe function. */ base = ioremap(res->start, resource_size(res)); if (!base) return -ENODEV; dram = mv_mbus_dram_info(); xhci_mvebu_mbus_config(base, dram); /* * This memory area was only needed to configure the MBus * windows, and is therefore no longer useful. */ iounmap(base); return 0; }
/* * Setup PCIE BARs and Address Decode Wins: * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks * WIN[0-3] -> DRAM bank[0-3] */ static void __init orion_pcie_setup_wins(void __iomem *base) { const struct mbus_dram_target_info *dram; u32 size; int i; dram = mv_mbus_dram_info(); /* * First, disable and clear BARs and windows. */ for (i = 1; i <= 2; i++) { writel(0, base + PCIE_BAR_CTRL_OFF(i)); writel(0, base + PCIE_BAR_LO_OFF(i)); writel(0, base + PCIE_BAR_HI_OFF(i)); } for (i = 0; i < 5; i++) { writel(0, base + PCIE_WIN04_CTRL_OFF(i)); writel(0, base + PCIE_WIN04_BASE_OFF(i)); writel(0, base + PCIE_WIN04_REMAP_OFF(i)); } writel(0, base + PCIE_WIN5_CTRL_OFF); writel(0, base + PCIE_WIN5_BASE_OFF); writel(0, base + PCIE_WIN5_REMAP_OFF); /* * Setup windows for DDR banks. Count total DDR size on the fly. */ size = 0; for (i = 0; i < dram->num_cs; i++) { const struct mbus_dram_window *cs = dram->cs + i; writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); writel(0, base + PCIE_WIN04_REMAP_OFF(i)); writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1, base + PCIE_WIN04_CTRL_OFF(i)); size += cs->size; } /* * Round up 'size' to the nearest power of two. */ if ((size & (size - 1)) != 0) size = 1 << fls(size); /* * Setup BAR[1] to all DRAM banks. */ writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); writel(0, base + PCIE_BAR_HI_OFF(1)); writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); }
static int __devinit ehci_orion_drv_probe(struct platform_device *pdev) { struct orion_ehci_data *pd = pdev->dev.platform_data; const struct mbus_dram_target_info *dram; struct resource *res; struct usb_hcd *hcd; struct ehci_hcd *ehci; void __iomem *regs; int irq, err; if (usb_disabled()) return -ENODEV; pr_debug("Initializing Orion-SoC USB Host Controller\n"); irq = platform_get_irq(pdev, 0); if (irq <= 0) { dev_err(&pdev->dev, "Found HC with no IRQ. Check %s setup!\n", dev_name(&pdev->dev)); err = -ENODEV; goto err1; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Found HC with no register addr. Check %s setup!\n", dev_name(&pdev->dev)); err = -ENODEV; goto err1; } if (!request_mem_region(res->start, resource_size(res), ehci_orion_hc_driver.description)) { dev_dbg(&pdev->dev, "controller already in use\n"); err = -EBUSY; goto err1; } regs = ioremap(res->start, resource_size(res)); if (regs == NULL) { dev_dbg(&pdev->dev, "error mapping memory\n"); err = -EFAULT; goto err2; } hcd = usb_create_hcd(&ehci_orion_hc_driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { err = -ENOMEM; goto err3; } hcd->rsrc_start = res->start; hcd->rsrc_len = resource_size(res); hcd->regs = regs; ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs + 0x100; ehci->regs = hcd->regs + 0x100 + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); hcd->has_tt = 1; ehci->sbrn = 0x20; /* * (Re-)program MBUS remapping windows if we are asked to. */ dram = mv_mbus_dram_info(); if (dram) ehci_orion_conf_mbus_windows(hcd, dram); /* * setup Orion USB controller. */ switch (pd->phy_version) { case EHCI_PHY_NA: /* dont change USB phy settings */ break; case EHCI_PHY_ORION: orion_usb_phy_v1_setup(hcd); break; case EHCI_PHY_DD: case EHCI_PHY_KW: default: printk(KERN_WARNING "Orion ehci -USB phy version isn't supported.\n"); } err = usb_add_hcd(hcd, irq, IRQF_SHARED); if (err) goto err4; return 0; err4: usb_put_hcd(hcd); err3: iounmap(regs); err2: release_mem_region(res->start, resource_size(res)); err1: dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), err); return err; }
static int sdhci_pxav3_probe(struct platform_device *pdev) { struct sdhci_pltfm_host *pltfm_host; struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; struct device *dev = &pdev->dev; struct device_node *np = pdev->dev.of_node; struct sdhci_host *host = NULL; struct sdhci_pxa *pxa = NULL; const struct of_device_id *match; int ret; host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, sizeof(*pxa)); if (IS_ERR(host)) return PTR_ERR(host); pltfm_host = sdhci_priv(host); pxa = sdhci_pltfm_priv(pltfm_host); pxa->clk_io = devm_clk_get(dev, "io"); if (IS_ERR(pxa->clk_io)) pxa->clk_io = devm_clk_get(dev, NULL); if (IS_ERR(pxa->clk_io)) { dev_err(dev, "failed to get io clock\n"); ret = PTR_ERR(pxa->clk_io); goto err_clk_get; } pltfm_host->clk = pxa->clk_io; clk_prepare_enable(pxa->clk_io); pxa->clk_core = devm_clk_get(dev, "core"); if (!IS_ERR(pxa->clk_core)) clk_prepare_enable(pxa->clk_core); /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR; if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { ret = armada_38x_quirks(pdev, host); if (ret < 0) goto err_mbus_win; ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); if (ret < 0) goto err_mbus_win; } match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); if (match) { ret = mmc_of_parse(host->mmc); if (ret) goto err_of_parse; sdhci_get_of_property(pdev); pdata = pxav3_get_mmc_pdata(dev); pdev->dev.platform_data = pdata; } else if (pdata) { /* on-chip device */ if (pdata->flags & PXA_FLAG_CARD_PERMANENT) host->mmc->caps |= MMC_CAP_NONREMOVABLE; /* If slot design supports 8 bit data, indicate this to MMC. */ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) host->mmc->caps |= MMC_CAP_8_BIT_DATA; if (pdata->quirks) host->quirks |= pdata->quirks; if (pdata->quirks2) host->quirks2 |= pdata->quirks2; if (pdata->host_caps) host->mmc->caps |= pdata->host_caps; if (pdata->host_caps2) host->mmc->caps2 |= pdata->host_caps2; if (pdata->pm_caps) host->mmc->pm_caps |= pdata->pm_caps; if (gpio_is_valid(pdata->ext_cd_gpio)) { ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio, 0); if (ret) { dev_err(mmc_dev(host->mmc), "failed to allocate card detect gpio\n"); goto err_cd_req; } } } pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); pm_suspend_ignore_children(&pdev->dev, 1); ret = sdhci_add_host(host); if (ret) { dev_err(&pdev->dev, "failed to add host\n"); goto err_add_host; } platform_set_drvdata(pdev, host); if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) device_init_wakeup(&pdev->dev, 1); pm_runtime_put_autosuspend(&pdev->dev); return 0; err_add_host: pm_runtime_disable(&pdev->dev); pm_runtime_put_noidle(&pdev->dev); err_of_parse: err_cd_req: err_mbus_win: clk_disable_unprepare(pxa->clk_io); clk_disable_unprepare(pxa->clk_core); err_clk_get: sdhci_pltfm_free(pdev); return ret; }
static int ehci_orion_drv_probe(struct platform_device *pdev) { struct orion_ehci_data *pd = dev_get_platdata(&pdev->dev); const struct mbus_dram_target_info *dram; struct resource *res; struct usb_hcd *hcd; struct ehci_hcd *ehci; void __iomem *regs; int irq, err; enum orion_ehci_phy_ver phy_version; struct orion_ehci_hcd *priv; if (usb_disabled()) return -ENODEV; pr_debug("Initializing Orion-SoC USB Host Controller\n"); irq = platform_get_irq(pdev, 0); if (irq <= 0) { dev_err(&pdev->dev, "Found HC with no IRQ. Check %s setup!\n", dev_name(&pdev->dev)); err = -ENODEV; goto err; } /* * Right now device-tree probed devices don't get dma_mask * set. Since shared usb code relies on it, set it here for * now. Once we have dma capability bindings this can go away. */ err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); if (err) goto err; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(regs)) { err = PTR_ERR(regs); goto err; } hcd = usb_create_hcd(&ehci_orion_hc_driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { err = -ENOMEM; goto err; } hcd->rsrc_start = res->start; hcd->rsrc_len = resource_size(res); hcd->regs = regs; ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs + 0x100; hcd->has_tt = 1; priv = hcd_to_orion_priv(hcd); /* * Not all platforms can gate the clock, so it is not an error if * the clock does not exists. */ priv->clk = devm_clk_get(&pdev->dev, NULL); if (!IS_ERR(priv->clk)) clk_prepare_enable(priv->clk); priv->phy = devm_phy_optional_get(&pdev->dev, "usb"); if (IS_ERR(priv->phy)) { err = PTR_ERR(priv->phy); goto err_phy_get; } else { err = phy_init(priv->phy); if (err) goto err_phy_init; err = phy_power_on(priv->phy); if (err) goto err_phy_power_on; } /* * (Re-)program MBUS remapping windows if we are asked to. */ dram = mv_mbus_dram_info(); if (dram) ehci_orion_conf_mbus_windows(hcd, dram); /* * setup Orion USB controller. */ if (pdev->dev.of_node) phy_version = EHCI_PHY_NA; else phy_version = pd->phy_version; switch (phy_version) { case EHCI_PHY_NA: /* dont change USB phy settings */ break; case EHCI_PHY_ORION: orion_usb_phy_v1_setup(hcd); break; case EHCI_PHY_DD: case EHCI_PHY_KW: default: dev_warn(&pdev->dev, "USB phy version isn't supported.\n"); } err = usb_add_hcd(hcd, irq, IRQF_SHARED); if (err) goto err_add_hcd; device_wakeup_enable(hcd->self.controller); return 0; err_add_hcd: if (!IS_ERR(priv->phy)) phy_power_off(priv->phy); err_phy_power_on: if (!IS_ERR(priv->phy)) phy_exit(priv->phy); err_phy_init: err_phy_get: if (!IS_ERR(priv->clk)) clk_disable_unprepare(priv->clk); usb_put_hcd(hcd); err: dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), err); return err; }
static int ehci_orion_drv_probe(struct platform_device *pdev) { struct orion_ehci_data *pd = pdev->dev.platform_data; const struct mbus_dram_target_info *dram; struct resource *res; struct usb_hcd *hcd; struct ehci_hcd *ehci; struct clk *clk; void __iomem *regs; int irq, err; enum orion_ehci_phy_ver phy_version; if (usb_disabled()) return -ENODEV; pr_debug("Initializing Orion-SoC USB Host Controller\n"); if (pdev->dev.of_node) irq = irq_of_parse_and_map(pdev->dev.of_node, 0); else irq = platform_get_irq(pdev, 0); if (irq <= 0) { dev_err(&pdev->dev, "Found HC with no IRQ. Check %s setup!\n", dev_name(&pdev->dev)); err = -ENODEV; goto err1; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Found HC with no register addr. Check %s setup!\n", dev_name(&pdev->dev)); err = -ENODEV; goto err1; } /* * Right now device-tree probed devices don't get dma_mask * set. Since shared usb code relies on it, set it here for * now. Once we have dma capability bindings this can go away. */ if (!pdev->dev.dma_mask) pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; if (!pdev->dev.coherent_dma_mask) pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); if (!request_mem_region(res->start, resource_size(res), ehci_orion_hc_driver.description)) { dev_dbg(&pdev->dev, "controller already in use\n"); err = -EBUSY; goto err1; } regs = ioremap(res->start, resource_size(res)); if (regs == NULL) { dev_dbg(&pdev->dev, "error mapping memory\n"); err = -EFAULT; goto err2; } /* Not all platforms can gate the clock, so it is not an error if the clock does not exists. */ clk = clk_get(&pdev->dev, NULL); if (!IS_ERR(clk)) { clk_prepare_enable(clk); clk_put(clk); } hcd = usb_create_hcd(&ehci_orion_hc_driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { err = -ENOMEM; goto err3; } hcd->rsrc_start = res->start; hcd->rsrc_len = resource_size(res); hcd->regs = regs; ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs + 0x100; hcd->has_tt = 1; /* * (Re-)program MBUS remapping windows if we are asked to. */ dram = mv_mbus_dram_info(); if (dram) ehci_orion_conf_mbus_windows(hcd, dram); /* * setup Orion USB controller. */ if (pdev->dev.of_node) phy_version = EHCI_PHY_NA; else phy_version = pd->phy_version; switch (phy_version) { case EHCI_PHY_NA: /* dont change USB phy settings */ break; case EHCI_PHY_ORION: orion_usb_phy_v1_setup(hcd); break; case EHCI_PHY_DD: case EHCI_PHY_KW: default: printk(KERN_WARNING "Orion ehci -USB phy version isn't supported.\n"); } err = usb_add_hcd(hcd, irq, IRQF_SHARED); if (err) goto err4; return 0; err4: usb_put_hcd(hcd); err3: if (!IS_ERR(clk)) { clk_disable_unprepare(clk); clk_put(clk); } iounmap(regs); err2: release_mem_region(res->start, resource_size(res)); err1: dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), err); return err; }