/*!
* This function is used to enable 26 mhz clock on CKO1. This pad
* is connected to MC13783 in order to derive all clocks
* needed to make sound work (bit clock and frame sync clock)
*/
static void mxc_init_pmic_clock(void)
{
mxc_ccm_modify_reg(MXC_CCM_COSR,
(MXC_CCM_COSR_CKO1EN | MXC_CCM_COSR_CKO1S_MASK |
MXC_CCM_COSR_CKO1DV_MASK),
MXC_CCM_COSR_CKO1EN | 0x01);
}
/*!
* Implementing steps required to transition to low-power modes
*
* @param mode The desired low-power mode. Possible values are,
* WAIT_MODE, DOZE_MODE, STOP_MODE or DSM_MODE
*
*/
void mxc_pm_lowpower(int mode)
{
unsigned int lpm, ipu_conf;
unsigned long reg;
local_irq_disable();
ipu_conf = __raw_readl(IPU_CONF);
switch (mode) {
case DOZE_MODE:
lpm = 1;
break;
case STOP_MODE:
/* State Retention mode */
lpm = 2;
__raw_writel(INT_GPT, AVIC_INTDISNUM);
__raw_writel(INT_GPIO1, AVIC_INTDISNUM);
/* work-around for SR mode after camera related test */
__raw_writel(0x51, IPU_CONF);
break;
case DSM_MODE:
/* Deep Sleep Mode */
lpm = 3;
/* Disable timer interrupt */
__raw_writel(INT_GPT, AVIC_INTDISNUM);
/* Enabled Well Bias
* SBYCS = 0, MCU clock source is disabled*/
mxc_ccm_modify_reg(MXC_CCM_CCMR,
MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_SBYCS,
MXC_CCM_CCMR_WBEN);
break;
default:
case WAIT_MODE:
/* Wait is the default mode used when idle. */
lpm = 0;
break;
}
reg = __raw_readl(MXC_CCM_CCMR);
reg = (reg & (~MXC_CCM_CCMR_LPM_MASK)) | lpm << MXC_CCM_CCMR_LPM_OFFSET;
__raw_writel(reg, MXC_CCM_CCMR);
/* Executing CP15 (Wait-for-Interrupt) Instruction */
/* wait for interrupt */
__asm__ __volatile__("mcr p15, 0, r1, c7, c0, 4\n"
"nop\n" "nop\n" "nop\n" "nop\n" "nop\n"::);
/* work-around for SR mode after camera related test */
__raw_writel(ipu_conf, IPU_CONF);
__raw_writel(INT_GPT, AVIC_INTENNUM);
__raw_writel(INT_GPIO1, AVIC_INTENNUM);
local_irq_enable();
}
/*!
* PLL clock scaling
*
* Change MCU PLL frequency and adjust derived clocks. Integer
* dividers are used generate the derived clocks so changed to produce
* the desired the valid frequencies are limited by the desired ARM
* frequency.
*
* The clock source for the MCU is set to the MCU PLL.
*
* @param arm_freq desired ARM frequency (Hz)
* @param max_freq desired MAX frequency (Hz)
* @param ip_freq desired IP frequency (Hz)
*
* @return Returns 0 on success or
* Returns non zero if error
* PLL_LESS_ARM_ERR if pll frequency is less than
* desired core frequency
* FREQ_OUT_OF_RANGE if desided frequencies ar not
* possible with the current mcu pll frequency.
*/
int mxc_pm_pllscale(long arm_freq, long max_freq, long ip_freq)
{
signed long pll_freq = 0; /* target pll frequency */
unsigned long old_pll;
unsigned long mask;
unsigned long value;
int ret_value;
printk(KERN_INFO "arm_freq=%ld, max_freq=%ld, ip_freq=%ld\n",
arm_freq, max_freq, ip_freq);
//print_frequencies();
do {
pll_freq += arm_freq;
if ((pll_freq > MCU_PLL_MAX_FREQ) || (pll_freq / 8 > arm_freq)) {
return FREQ_OUT_OF_RANGE;
}
if (pll_freq < MCU_PLL_MIN_FREQ) {
ret_value = 111;
} else {
ret_value =
cal_pdr0_value(pll_freq, arm_freq, max_freq,
ip_freq, &mask, &value);
}
} while (ret_value != 0);
old_pll = clk_get_rate(mcu_pll_clk);
if (pll_freq > old_pll) {
/* if pll freq is increasing then change dividers first */
mxc_ccm_modify_reg(MXC_CCM_PDR0, mask, value);
ret_value = clk_set_rate(mcu_pll_clk, pll_freq);
} else {
/* if pll freq is decreasing then change pll first */
ret_value = clk_set_rate(mcu_pll_clk, pll_freq);
mxc_ccm_modify_reg(MXC_CCM_PDR0, mask, value);
}
//print_frequencies();
return ret_value;
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
mxc_cpu_common_init();
/* Enable 26 mhz clock on CKO1 for MC13783 audio */
mxc_ccm_modify_reg(MXC_CCM_COSR, 0x00000fff, 0x00000208);
mxc_gpio_init();
mx31ads_gpio_init();
mxc_expio_init();
mxc_init_keypad();
mxc_init_extuart();
mxc_init_nor_mtd();
mxc_init_nand_mtd();
}
