static inline void mxc_init_dptc(void)
{
if (clk_get_rate(ckih_clk) == 27000000
&& mxc_cpu_is_rev(CHIP_REV_2_0) < 0) {
mxc_dptc_device.dev.platform_data = &dptc_wp_allfreq_27ckih;
} else if (clk_get_rate(ckih_clk) == 26000000
&& mxc_cpu_is_rev(CHIP_REV_2_0)) {
mxc_dptc_device.dev.platform_data =
&dptc_wp_allfreq_26ckih_TO_2_0;
}
(void)platform_device_register(&mxc_dptc_device);
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value, register_mask;
printk("Initializing regulators for Sharp Netwalker.\n");
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
sw2_init.constraints.state_mem.uV = 1100000;
else if (mxc_cpu_is_rev(CHIP_REV_2_0) >= 1) {
sw2_init.constraints.state_mem.uV = 1250000;
sw1_init.constraints.state_mem.uV = 1000000;
}
/* Enable coin cell charger */
value = BITFVAL(CIONCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(CIONCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
// mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
// mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
// mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
// mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
// mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
// mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
// mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
// mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
// mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
// mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
// mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
// mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
// mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
// mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
// mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
regulator_has_full_constraints();
return 0;
}
static inline void mxc_init_dptc(void)
{
if (clk_get_rate(ckih_clk) == 27000000) {
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
dptc_data.dptc_wp_allfreq = NULL;
else
dptc_data.dptc_wp_allfreq =
dptc_wp_allfreq_27ckih_TO_2_0;
} else if (clk_get_rate(ckih_clk) == 26000000
&& mxc_cpu_is_rev(CHIP_REV_2_0) == 1) {
dptc_data.dptc_wp_allfreq = dptc_wp_allfreq_26ckih_TO_2_0;
}
(void)platform_device_register(&mxc_dptc_device);
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value;
pmic_event_callback_t power_key_event;
int register_mask;
printk("Initializing regulators for 3-stack.\n");
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
sw2_init.constraints.state_mem.uV = 1100000;
/* subscribe PWRON1 event to enable ON_OFF key */
power_key_event.param = NULL;
power_key_event.func = (void *)power_on_evt_handler;
pmic_event_subscribe(EVENT_PWRONI, power_key_event);
/* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */
pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff);
value |= 0x000010;
pmic_write_reg(REG_POWER_CTL0, value, 0xffffff);
/* Set the STANDBYSECINV bit, so that STANDBY pin is
* interpreted as active low.
*/
value = BITFVAL(STANDBYSECINV, 1);
register_mask = BITFMASK(STANDBYSECINV);
pmic_write_reg(REG_POWER_CTL2, value, register_mask);
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
return 0;
}
static int mx51_suspend_enter(suspend_state_t state)
{
if (gpc_dvfs_clk == NULL)
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
/* gpc clock is needed for SRPG */
clk_enable(gpc_dvfs_clk);
switch (state) {
case PM_SUSPEND_MEM:
mxc_cpu_lp_set(STOP_POWER_OFF);
break;
case PM_SUSPEND_STANDBY:
mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
break;
default:
return -EINVAL;
}
if (tzic_enable_wake(0) != 0)
return -EAGAIN;
if (state == PM_SUSPEND_MEM) {
cpu_do_suspend_workaround();
/*clear the EMPGC0/1 bits */
__raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
} else {
if ((mxc_cpu_is_rev(CHIP_REV_2_0)) < 0) {
/* do cpu_idle_workaround */
u32 l2_iram_addr = IDLE_IRAM_BASE_ADDR;
if (!iram_ready)
return 0;
if (l2_iram_addr > 0x1FFE8000)
cpu_cortexa8_do_idle(IO_ADDRESS(l2_iram_addr));
} else {
cpu_do_idle();
}
}
clk_disable(gpc_dvfs_clk);
return 0;
}
/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
void arch_idle(void)
{
if (likely(!mxc_jtag_enabled)) {
if (gpc_dvfs_clk == NULL)
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
/* gpc clock is needed for SRPG */
clk_enable(gpc_dvfs_clk);
mxc_cpu_lp_set(arch_idle_mode);
if ((mxc_cpu_is_rev(CHIP_REV_2_0)) < 0) {
u32 l2_iram_addr = IDLE_IRAM_BASE_ADDR;
if (!iram_ready)
return;
if (l2_iram_addr > 0x1FFE8000)
cpu_cortexa8_do_idle(IO_ADDRESS(l2_iram_addr));
} else {
cpu_do_idle();
}
clk_disable(gpc_dvfs_clk);
}
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value, register_mask;
printk("Initializing regulators for Babbage.\n");
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
sw2_init.constraints.state_mem.uV = 1100000;
else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) {
sw2_init.constraints.state_mem.uV = 1250000;
sw1_init.constraints.state_mem.uV = 1000000;
}
/* enable standby controll for all regulators */
pmic_read_reg(REG_MODE_0, &value, 0xffffff);
value |= REG_MODE_0_ALL_MASK;
pmic_write_reg(REG_MODE_0, value, 0xffffff);
pmic_read_reg(REG_MODE_1, &value, 0xffffff);
value |= REG_MODE_1_ALL_MASK;
pmic_write_reg(REG_MODE_1, value, 0xffffff);
/* enable switch audo mode */
pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff);
/* only for mc13892 2.0A */
if ((value & 0x0000FFFF) == 0x45d0) {
pmic_read_reg(REG_SW_4, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW1MODE_LSB) |
(SWMODE_MASK << SW2MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW1MODE_LSB) |
(SWMODE_AUTO << SW2MODE_LSB);
pmic_write_reg(REG_SW_4, value, 0xffffff);
pmic_read_reg(REG_SW_5, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW3MODE_LSB) |
(SWMODE_MASK << SW4MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW3MODE_LSB) |
(SWMODE_AUTO << SW4MODE_LSB);
pmic_write_reg(REG_SW_5, value, 0xffffff);
}
/* Enable coin cell charger */
value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
regulator_has_full_constraints();
return 0;
}