static void __init mx25_init_irq(void)
{
struct device_node *np;
void __iomem *avic_base;
np = of_find_compatible_node(NULL, NULL, "fsl,avic");
avic_base = of_iomap(np, 0);
BUG_ON(!avic_base);
mxc_init_irq(avic_base);
}
static int mx31_suspend_enter(suspend_state_t state)
{
unsigned long reg;
/* Enable Well Bias and set VSTBY
* VSTBY pin will be asserted during SR mode. This asks the
* PM IC to set the core voltage to the standby voltage
* Must clear the MXC_CCM_CCMR_SBYCS bit as well?? */
reg = __raw_readl(MXC_CCM_CCMR);
reg &= ~MXC_CCM_CCMR_LPM_MASK;
reg |= MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY | MXC_CCM_CCMR_SBYCS;
switch (state) {
case PM_SUSPEND_MEM:
/* State Retention mode */
reg |= 2 << MXC_CCM_CCMR_LPM_OFFSET;
__raw_writel(reg, MXC_CCM_CCMR);
/* Executing CP15 (Wait-for-Interrupt) Instruction */
cpu_do_idle();
break;
case PM_SUSPEND_STANDBY:
/* Deep Sleep Mode */
reg |= 3 << MXC_CCM_CCMR_LPM_OFFSET;
__raw_writel(reg, MXC_CCM_CCMR);
/* wake up by keypad */
reg = __raw_readl(MXC_CCM_WIMR);
reg &= ~(1 << 18);
__raw_writel(reg, MXC_CCM_WIMR);
flush_cache_all();
l2x0_disable();
mxc_pm_arch_entry(MX31_IO_ADDRESS(MX31_NFC_BASE_ADDR), 2048);
printk(KERN_INFO "Resume from DSM\n");
l2x0_enable();
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
break;
default:
return -EINVAL;
}
return 0;
}
void __init mx21_init_irq(void)
{
mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
}
void __init mx31_init_irq(void)
{
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
}
void __init mx31ads_init_irq(void)
{
mxc_init_irq();
mx31ads_init_expio();
}
void __init mx25_init_irq(void)
{
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
imx25_register_gpios();
}
void __init mxc91231_init_irq(void)
{
mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
}
void __init mx25_init_irq(void)
{
mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
}
void __init mx27_init_irq(void)
{
mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}