static void __init mx31_3ds_init(void) { int ret; imx31_soc_init(); /* Configure SPI1 IOMUX */ mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); imx31_add_imx_uart0(&uart_pdata); imx31_add_mxc_nand(&mx31_3ds_nand_board_info); imx31_add_spi_imx1(&spi1_pdata); spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); platform_add_devices(devices, ARRAY_SIZE(devices)); imx31_add_imx_keypad(&mx31_3ds_keymap_data); mx31_3ds_usbotg_init(); if (otg_mode_host) { otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); if (otg_pdata.otg) imx31_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); if (usbh2_pdata.otg) imx31_add_mxc_ehci_hs(2, &usbh2_pdata); if (!otg_mode_host) imx31_add_fsl_usb2_udc(&usbotg_pdata); if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) printk(KERN_WARNING "Init of the debug board failed, all " "devices on the debug board are unusable.\n"); imx31_add_imx2_wdt(NULL); imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); imx31_add_mxc_mmc(0, &sdhc1_pdata); imx31_add_spi_imx0(&spi0_pdata); imx31_add_ipu_core(&mx3_ipu_data); imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* CSI */ /* Camera power: default - off */ ret = gpio_request_array(mx31_3ds_camera_gpios, ARRAY_SIZE(mx31_3ds_camera_gpios)); if (ret) { pr_err("Failed to request camera gpios"); iclink_ov2640.power = NULL; } mx31_3ds_init_camera(); }
static int usbh2_init(struct platform_device *pdev) { int err; mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); mxc_iomux_set_gpr(MUX_PGP_UH2, true); /* Enable the chip */ err = gpio_request(USBH2_CS, "USB-H2-CS"); if (err) { pr_err("Failed to request the usb host 2 CS gpio\n"); return err; } err = gpio_direction_output(USBH2_CS, 0/*Enabled*/); if (err) { pr_err("Failed to drive the usb host 2 CS gpio\n"); goto h2_free_cs; } /* H2 phy reset*/ err = gpio_request(USBH2_RESET, "USB-H2-RESET"); if (err) { pr_err("Failed to request the usb host 2 reset gpio\n"); goto h2_free_cs; } err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/); if (err) { pr_err("Failed to reset the usb host 2 phy\n"); goto h2_free_reset; } gpio_set_value(USBH2_RESET, 0/*LOW*/); mdelay(5); gpio_set_value(USBH2_RESET, 1/*HIGH*/); mdelay(10); return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI); h2_free_reset: gpio_free(USBH2_RESET); h2_free_cs: gpio_free(USBH2_CS); return err; }
static int usbh1_init(struct platform_device *pdev) { int pins[] = { MX31_PIN_CSPI1_MOSI__USBH1_RXDM, MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, }; mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1"); mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); mdelay(10); return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI); }
static void __init qong_init_nand_mtd(void) { /* init CS */ __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); /* enable pin */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO)); if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable")) gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); /* ready/busy pin */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO)); if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy")) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB)); /* write protect pin */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO)); if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp")) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B)); platform_device_register(&qong_nand_device); }
static int moboard_usbh2_hw_init(struct platform_device *pdev) { int ret = gpio_request(USBH2_EN_B, "usbh2-en"); if (ret) return ret; mxc_iomux_set_gpr(MUX_PGP_UH2, true); mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); gpio_direction_output(USBH2_EN_B, 0); return 0; }
static int usbh1_init(struct platform_device *pdev) { int pins[] = { MX31_PIN_CSPI1_MOSI__USBH1_RXDM, MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, }; mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1"); mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); return 0; }
static void __init mx31_3ds_init(void) { imx31_soc_init(); /* Configure SPI1 IOMUX */ mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); imx31_add_imx_uart0(&uart_pdata); imx31_add_mxc_nand(&mx31_3ds_nand_board_info); imx31_add_spi_imx1(&spi1_pdata); imx31_add_imx_keypad(&mx31_3ds_keymap_data); imx31_add_imx2_wdt(); imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); imx31_add_spi_imx0(&spi0_pdata); imx31_add_ipu_core(); imx31_add_mx3_sdc_fb(&mx3fb_pdata); imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata); imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); }
static int usbotg_init(struct platform_device *pdev) { unsigned int pins[] = { MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, }; mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG"); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true); mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true); /* chip select */ mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO), "USBOTG_CS"); gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS"); gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0); return 0; }
/*! * Configure the IOMUX GPR register to receive shared SDMA UART events * * @param port a UART port */ void config_uartdma_event(int port) { switch (port) { case 1: /* Configure to receive UART 2 SDMA events */ mxc_iomux_set_gpr(MUX_PGP_FIRI, false); break; case 2: /* Configure to receive UART 3 SDMA events */ mxc_iomux_set_gpr(MUX_CSPI1_UART3, true); break; case 4: /* Configure to receive UART 5 SDMA events */ mxc_iomux_set_gpr(MUX_CSPI3_UART5_SEL, true); break; default: break; } }
static int devboard_usbh1_hw_init(struct platform_device *pdev) { mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); return 0; }
static int devboard_usbh1_hw_init(struct platform_device *pdev) { mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); mdelay(10); return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI); }
static void usb_xcvr_reset(void) { mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_gpr(MUX_PGP_UH2, true); mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD); gpio_request(OTG_EN_B, "usb-udc-en"); gpio_direction_output(OTG_EN_B, 0); gpio_request(USBH2_EN_B, "usbh2-en"); gpio_direction_output(USBH2_EN_B, 0); gpio_request(USB_RESET_B, "usb-reset"); gpio_direction_output(USB_RESET_B, 0); mdelay(1); gpio_set_value(USB_RESET_B, 1); mdelay(1); }
static int usbh2_init(struct platform_device *pdev) { int pins[] = { MX31_PIN_USBH2_DATA0__USBH2_DATA0, MX31_PIN_USBH2_DATA1__USBH2_DATA1, MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR, MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP, }; mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); mxc_iomux_set_gpr(MUX_PGP_UH2, true); /* chip select */ mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), "USBH2_CS"); gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); mdelay(10); return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); }
/* * Board specific initialization. */ static void __init pcm037_init(void) { int ret; imx31_soc_init(); mxc_iomux_set_gpr(MUX_PGP_UH2, 1); mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), "pcm037"); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ if (pcm037_variant() == PCM037_EET) mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); else mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins, ARRAY_SIZE(pcm037_uart1_handshake_pins), "pcm037_uart1"); platform_add_devices(devices, ARRAY_SIZE(devices)); imx31_add_imx2_wdt(NULL); imx31_add_imx_uart0(&uart_pdata); /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ imx31_add_imx_uart1(&uart_pdata); imx31_add_imx_uart2(&uart_pdata); imx31_add_mxc_w1(NULL); /* LAN9217 IRQ pin */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); if (ret) pr_warning("could not get LAN irq gpio\n"); else { gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); platform_device_register(&pcm037_eth); } /* I2C adapters and devices */ i2c_register_board_info(1, pcm037_i2c_devices, ARRAY_SIZE(pcm037_i2c_devices)); imx31_add_imx_i2c1(&pcm037_i2c1_data); imx31_add_imx_i2c2(&pcm037_i2c2_data); imx31_add_mxc_nand(&pcm037_nand_board_info); imx31_add_mxc_mmc(0, &sdhc_pdata); imx31_add_ipu_core(&mx3_ipu_data); imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* CSI */ /* Camera power: default - off */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power"); if (!ret) gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1); else iclink_mt9t031.power = NULL; pcm037_init_camera(); platform_device_register(&pcm970_sja1000); if (otg_mode_host) { otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); if (otg_pdata.otg) imx31_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); if (usbh2_pdata.otg) imx31_add_mxc_ehci_hs(2, &usbh2_pdata); if (!otg_mode_host) imx31_add_fsl_usb2_udc(&otg_device_pdata); }
/* * Board specific initialization. */ static void __init mxc_board_init(void) { int ret; u32 tmp; mxc_iomux_set_gpr(MUX_PGP_UH2, 1); mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), "pcm037"); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ if (pcm037_variant() == PCM037_EET) mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); else mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins, ARRAY_SIZE(pcm037_uart1_handshake_pins), "pcm037_uart1"); platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_uart_device1, &uart_pdata); mxc_register_device(&mxc_uart_device2, &uart_pdata); mxc_register_device(&mxc_w1_master_device, NULL); /* LAN9217 IRQ pin */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); if (ret) pr_warning("could not get LAN irq gpio\n"); else { gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); platform_device_register(&pcm037_eth); } /* I2C adapters and devices */ i2c_register_board_info(1, pcm037_i2c_devices, ARRAY_SIZE(pcm037_i2c_devices)); mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data); mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data); mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); /* CSI */ /* Camera power: default - off */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power"); if (!ret) gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1); else iclink_mt9t031.power = NULL; if (!pcm037_camera_alloc_dma(4 * 1024 * 1024)) mxc_register_device(&mx3_camera, &camera_pdata); platform_device_register(&pcm970_sja1000); #if defined(CONFIG_USB_ULPI) if (otg_mode_host) { otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); mxc_register_device(&mxc_otg_host, &otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); mxc_register_device(&mxc_usbh2, &usbh2_pdata); #endif if (!otg_mode_host) mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); }
/*! * Setup GPIO for ATA interface * */ void gpio_ata_active(void) { /* * Configure the GPR for ATA group B signals */ mxc_iomux_set_gpr(MUX_PGP_ATA_8 | MUX_PGP_ATA_5 | MUX_PGP_ATA_4 | MUX_PGP_ATA_3 | MUX_PGP_ATA_2, false); mxc_iomux_set_gpr(MUX_PGP_ATA_9 | MUX_PGP_ATA_7 | MUX_PGP_ATA_6 | MUX_PGP_ATA_1, true); /* * Configure the IOMUX for ATA group B signals */ mxc_request_iomux(MX31_PIN_CSPI1_MOSI, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D0 mxc_request_iomux(MX31_PIN_CSPI1_MISO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D1 mxc_request_iomux(MX31_PIN_CSPI1_SS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D2 mxc_request_iomux(MX31_PIN_CSPI1_SS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D3 mxc_request_iomux(MX31_PIN_CSPI1_SS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D4 mxc_request_iomux(MX31_PIN_CSPI1_SCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D5 mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D6 mxc_request_iomux(MX31_PIN_STXD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D7 mxc_request_iomux(MX31_PIN_SRXD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D8 mxc_request_iomux(MX31_PIN_SCK3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D9 mxc_request_iomux(MX31_PIN_SFS3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D10 mxc_request_iomux(MX31_PIN_STXD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D11 mxc_request_iomux(MX31_PIN_SRXD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D12 mxc_request_iomux(MX31_PIN_SCK6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D13 mxc_request_iomux(MX31_PIN_CAPTURE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D14 mxc_request_iomux(MX31_PIN_COMPARE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D15 /* Config the multiplex pin of ATA interface DIR, DA0-2, INTRQ, DMARQ */ mxc_request_iomux(MX31_PIN_KEY_COL4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DMARQ_B mxc_request_iomux(MX31_PIN_KEY_ROW6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_INTRQ_B mxc_request_iomux(MX31_PIN_KEY_COL5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA0 mxc_request_iomux(MX31_PIN_KEY_COL6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA1 mxc_request_iomux(MX31_PIN_KEY_COL7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA2 mxc_request_iomux(MX31_PIN_KEY_ROW7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_BUFFER_DIR /* HDD_ENABLE_B(H:Disable,L:Enable) */ mxc_request_iomux(MX31_PIN_CSI_D4, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); // HDD_ENABLE_B mxc_set_gpio_direction(MX31_PIN_CSI_D4, 0); mdelay(10); mxc_set_gpio_dataout(MX31_PIN_CSI_D4, 0); mdelay(10); /* These ATA pins are common to Group A and Group B */ mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); mxc_request_iomux(MX31_PIN_PWMO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* Need fast slew rate for UDMA mode */ #define ATA_DAT_PAD_CFG (PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE | PAD_CTL_100K_PU) mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, ATA_DAT_PAD_CFG); // data 0 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, ATA_DAT_PAD_CFG); // data 1 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, ATA_DAT_PAD_CFG); // data 2 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, ATA_DAT_PAD_CFG); // data 3 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, ATA_DAT_PAD_CFG); // data 4 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, ATA_DAT_PAD_CFG); // data 5 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, ATA_DAT_PAD_CFG); // data 6 mxc_iomux_set_pad(MX31_PIN_STXD3, ATA_DAT_PAD_CFG); // data 7 mxc_iomux_set_pad(MX31_PIN_SRXD3, ATA_DAT_PAD_CFG); // data 8 mxc_iomux_set_pad(MX31_PIN_SCK3, ATA_DAT_PAD_CFG); // data 9 mxc_iomux_set_pad(MX31_PIN_SFS3, ATA_DAT_PAD_CFG); // data 10 mxc_iomux_set_pad(MX31_PIN_STXD6, ATA_DAT_PAD_CFG); // data 11 mxc_iomux_set_pad(MX31_PIN_SRXD6, ATA_DAT_PAD_CFG); // data 12 mxc_iomux_set_pad(MX31_PIN_SCK6, ATA_DAT_PAD_CFG); // data 13 mxc_iomux_set_pad(MX31_PIN_CAPTURE, ATA_DAT_PAD_CFG); // data 14 mxc_iomux_set_pad(MX31_PIN_COMPARE, ATA_DAT_PAD_CFG); // data 15 #undef ATA_DAT_PAD_CFG #define ATA_CTL_PAD_CFG (PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE) mxc_iomux_set_pad(MX31_PIN_KEY_COL4, ATA_CTL_PAD_CFG); // ATA_DMARQ); mxc_iomux_set_pad(MX31_PIN_KEY_ROW6, ATA_CTL_PAD_CFG); // ATA_INTRQ); mxc_iomux_set_pad(MX31_PIN_KEY_COL5, ATA_CTL_PAD_CFG); // mxc_iomux_set_pad(MX31_PIN_KEY_COL6, ATA_CTL_PAD_CFG); // mxc_iomux_set_pad(MX31_PIN_KEY_COL7, ATA_CTL_PAD_CFG); // mxc_iomux_set_pad(MX31_PIN_KEY_ROW7, ATA_CTL_PAD_CFG); // mxc_iomux_set_pad(MX31_PIN_ATA_CS0, ATA_CTL_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_ATA_CS1, ATA_CTL_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_ATA_DIOR, ATA_CTL_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_ATA_DIOW, ATA_CTL_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_ATA_DMACK, ATA_CTL_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_ATA_RESET_B, ATA_CTL_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_PWMO, ATA_CTL_PAD_CFG); #undef ATA_CTL_PAD_CFG }