static int init_panel(struct device *dev, dma_addr_t phys, int memsize, struct mxs_platform_fb_entry *pentry) { int ret = 0; lcd_clk = clk_get(dev, "dis_lcdif"); if (IS_ERR(lcd_clk)) { ret = PTR_ERR(lcd_clk); goto out; } ret = clk_enable(lcd_clk); if (ret) { clk_put(lcd_clk); goto out; } ret = clk_set_rate(lcd_clk, 1000000 / pentry->cycle_time_ns); /* kHz */ if (ret) { clk_disable(lcd_clk); clk_put(lcd_clk); goto out; } /* * Make sure we do a high-to-low transition to reset the panel. * First make it low for 100 msec, hi for 10 msec, low for 10 msec, * then hi. */ __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ mdelay(100); __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ mdelay(10); __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ /* For the Samsung, Reset must be held low at least 30 uSec * Therefore, we'll hold it low for about 10 mSec just to be sure. * Then we'll wait 1 mSec afterwards. */ mdelay(10); __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ mdelay(1); setup_dotclk_panel(DOTCLK_V_PULSE_WIDTH, DOTCLK_V_PERIOD, DOTCLK_V_WAIT_CNT, DOTCLK_V_ACTIVE, DOTCLK_H_PULSE_WIDTH, DOTCLK_H_PERIOD, DOTCLK_H_WAIT_CNT, DOTCLK_H_ACTIVE, 0); ret = mxs_lcdif_dma_init(dev, phys, memsize); if (ret) goto out; mxs_lcd_set_bl_pdata(pentry->bl_data); mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry); return 0; out: return ret; }
static int init_panel(struct device *dev, dma_addr_t phys, int memsize, struct mxs_platform_fb_entry *pentry) { int ret = 0; lcd_clk = clk_get(NULL, "lcdif"); if (IS_ERR(lcd_clk)) { ret = PTR_ERR(lcd_clk); goto out; } ret = clk_enable(lcd_clk); if (ret) { clk_put(lcd_clk); goto out; } ret = clk_set_rate(lcd_clk, 1000000000 / pentry->cycle_time_ns); /* Hz */ if (ret) { clk_disable(lcd_clk); clk_put(lcd_clk); goto out; } setup_dotclk_panel_8bit(DOTCLK_V_PULSE_WIDTH, DOTCLK_V_PERIOD, DOTCLK_V_WAIT_CNT, DOTCLK_V_ACTIVE, DOTCLK_H_PULSE_WIDTH, DOTCLK_H_PERIOD, DOTCLK_H_WAIT_CNT, DOTCLK_H_ACTIVE, 0); ret = mxs_lcdif_dma_init(dev, phys, memsize); if (ret) goto out; mxs_lcd_set_bl_pdata(pentry->bl_data); mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry); return 0; out: return ret; }
static int init_panel(struct device *dev, dma_addr_t phys, int memsize, struct mxs_platform_fb_entry *pentry) { DBG_PRINT("%s , line:%d\n", __FUNCTION__, __LINE__); int ret = 0; lcd_clk = clk_get(dev, "dis_lcdif"); if (IS_ERR(lcd_clk)) { ret = PTR_ERR(lcd_clk); goto out; } ret = clk_enable(lcd_clk); if (ret) { clk_put(lcd_clk); goto out; } ret = clk_set_rate(lcd_clk, 1000000 / pentry->cycle_time_ns); /* kHz */ if (ret) { clk_disable(lcd_clk); clk_put(lcd_clk); goto out; } mxs_elcdif_mpu_setup_interface(); /* * Make sure we do a high-to-low transition to reset the panel. * First make it low for 100 msec, hi for 10 msec, low for 10 msec, * then hi. */ __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ msleep(10); __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ msleep(10); __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ /* For the Samsung, Reset must be held low at least 30 uSec * Therefore, we'll hold it low for about 10 mSec just to be sure. * Then we'll wait 1 mSec afterwards. */ msleep(5); __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ msleep(30); WriteLCDReg(0x0007, 0x0131); // Set D1=0, D0=1 msleep(5); WriteLCDReg(0x0007, 0x0130); // Set D1=0, D0=0 msleep(5); WriteLCDReg(0x0007, 0x0000); // display OFF //setup MCU mode DBG_PRINT("%s , line:%d\n", __FUNCTION__, __LINE__); ret = mxs_lcdif_dma_init(dev, phys, memsize); if (ret) goto out; DBG_PRINT("%s , line:%d\n", __FUNCTION__, __LINE__); mxs_lcd_set_bl_pdata(pentry->bl_data); mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry); //*************Power On sequence ******************// WriteLCDReg(0x0010, 0x0080); // SAP, BT[3:0], AP, DSTB, SLP msleep(20); // Dis-charge capacitor power voltage WriteLCDReg(0x0010, 0x1190); // SAP, BT[3:0], AP, DSTB, SLP, STB WriteLCDReg(0x0011, 0x0227); // DC1[2:0], DC0[2:0], VC[2:0] msleep(30); // Delay 50ms WriteLCDReg(0x0012, 0x008c); //Inernal reference voltage =Vci; msleep(5); // Delay 50ms WriteLCDReg(0x0013, 0x1900); // VDV[4:0] for VCOM amplitude WriteLCDReg(0x0029, 0x0020); // VCM[5:0] for VCOMH msleep(5); // Delay 50ms WriteLCDReg(0x0007, 0x0133); // 262K color and display ON setup_mcu_panel(); panel_init = 1; return 0; out: panel_init = 0; return ret; }