/* timing set */ static int nxp_nand_timing_set(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; uint32_t ret, mode; ret = onfi_get_async_timing_mode(chip); if (ret == ONFI_TIMING_MODE_UNKNOWN) { NX_MCUS_SetNANDBUSConfig ( 0, /* NF */ CFG_SYS_NAND_TACS, // tACS ( 0 ~ 3 ) CFG_SYS_NAND_TCAH, // tCAH ( 0 ~ 3 ) CFG_SYS_NAND_TCOS, // tCOS ( 0 ~ 3 ) CFG_SYS_NAND_TCOH, // tCOH ( 0 ~ 3 ) CFG_SYS_NAND_TACC // tACC ( 1 ~ 16) ); return 0; } mode = fls(ret) - 1; TM_DBGOUT("ONFI TIMING MODE (%d) \n", mode); nand_onfi_timing_set (mtd, mode); return 0; }
/* queries the NAND device to see what ONFI modes it supports. */ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) { int i; /* we needn't to do a reset here because driver has already * reset all the banks before * */ if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & ONFI_TIMING_MODE__VALUE)) return FAIL; for (i = 5; i > 0; i--) { if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & (0x01 << i)) break; } nand_onfi_timing_set(denali, i); /* By now, all the ONFI devices we know support the page cache */ /* rw feature. So here we enable the pipeline_rw_ahead feature */ /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ return PASS; }
/* queries the NAND device to see what ONFI modes it supports. */ static uint32_t get_onfi_nand_para(struct denali_nand_info *denali) { int i; /* * we needn't to do a reset here because driver has already * reset all the banks before */ if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) & ONFI_TIMING_MODE__VALUE)) return -EIO; for (i = 5; i > 0; i--) { if (readl(denali->flash_reg + ONFI_TIMING_MODE) & (0x01 << i)) break; } nand_onfi_timing_set(denali, i); /* * By now, all the ONFI devices we know support the page cache * rw feature. So here we enable the pipeline_rw_ahead feature */ return 0; }
static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) { uint16_t status = PASS; uint32_t id_bytes[8], addr; uint8_t maf_id, device_id; int i; /* * Use read id method to get device ID and other params. * For some NAND chips, controller can't report the correct * device ID by reading from DEVICE_ID register */ addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, 0x90); index_addr(denali, addr | 1, 0); for (i = 0; i < 8; i++) index_addr_read_data(denali, addr | 2, &id_bytes[i]); maf_id = id_bytes[0]; device_id = id_bytes[1]; if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ if (FAIL == get_onfi_nand_para(denali)) return FAIL; } else if (maf_id == 0xEC) { /* Samsung NAND */ get_samsung_nand_para(denali, device_id); } else if (maf_id == 0x98) { /* Toshiba NAND */ get_toshiba_nand_para(denali); } else if (maf_id == 0xAD) { /* Hynix NAND */ get_hynix_nand_para(denali, device_id); } dev_info(denali->dev, "Dump timing register values:\n" "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", ioread32(denali->flash_reg + ACC_CLKS), ioread32(denali->flash_reg + RE_2_WE), ioread32(denali->flash_reg + RE_2_RE), ioread32(denali->flash_reg + WE_2_RE), ioread32(denali->flash_reg + ADDR_2_DATA), ioread32(denali->flash_reg + RDWR_EN_LO_CNT), ioread32(denali->flash_reg + RDWR_EN_HI_CNT), ioread32(denali->flash_reg + CS_SETUP_CNT)); find_valid_banks(denali); detect_partition_feature(denali); /* * If the user specified to override the default timings * with a specific ONFI mode, we apply those changes here. */ if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) nand_onfi_timing_set(denali, onfi_timing_mode); return status; }
static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) { uint16_t status = PASS; uint32_t id_bytes[5], addr; uint8_t i, maf_id, device_id; dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", __FILE__, __LINE__, __func__); addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); index_addr(denali, (uint32_t)addr | 0, 0x90); index_addr(denali, (uint32_t)addr | 1, 0); for (i = 0; i < 5; i++) index_addr_read_data(denali, addr | 2, &id_bytes[i]); maf_id = id_bytes[0]; device_id = id_bytes[1]; if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { if (FAIL == get_onfi_nand_para(denali)) return FAIL; } else if (maf_id == 0xEC) { get_samsung_nand_para(denali, device_id); } else if (maf_id == 0x98) { get_toshiba_nand_para(denali); } else if (maf_id == 0xAD) { get_hynix_nand_para(denali, device_id); } dev_info(denali->dev, "Dump timing register values:" "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", ioread32(denali->flash_reg + ACC_CLKS), ioread32(denali->flash_reg + RE_2_WE), ioread32(denali->flash_reg + RE_2_RE), ioread32(denali->flash_reg + WE_2_RE), ioread32(denali->flash_reg + ADDR_2_DATA), ioread32(denali->flash_reg + RDWR_EN_LO_CNT), ioread32(denali->flash_reg + RDWR_EN_HI_CNT), ioread32(denali->flash_reg + CS_SETUP_CNT)); find_valid_banks(denali); detect_partition_feature(denali); if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) nand_onfi_timing_set(denali, onfi_timing_mode); return status; }
static uint32_t denali_nand_timing_set(struct denali_nand_info *denali) { uint32_t id_bytes[8], addr; uint8_t maf_id, device_id; int i; /* * Use read id method to get device ID and other params. * For some NAND chips, controller can't report the correct * device ID by reading from DEVICE_ID register */ addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, 0x90); index_addr(denali, addr | 1, 0); for (i = 0; i < 8; i++) index_addr_read_data(denali, addr | 2, &id_bytes[i]); maf_id = id_bytes[0]; device_id = id_bytes[1]; if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ if (get_onfi_nand_para(denali)) return -EIO; } else if (maf_id == 0xEC) { /* Samsung NAND */ get_samsung_nand_para(denali, device_id); } else if (maf_id == 0x98) { /* Toshiba NAND */ get_toshiba_nand_para(denali); } else if (maf_id == 0xAD) { /* Hynix NAND */ get_hynix_nand_para(denali, device_id); } find_valid_banks(denali); detect_partition_feature(denali); /* * If the user specified to override the default timings * with a specific ONFI mode, we apply those changes here. */ if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) nand_onfi_timing_set(denali, onfi_timing_mode); return 0; }
static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) { int i; if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & ONFI_TIMING_MODE__VALUE)) return FAIL; for (i = 5; i > 0; i--) { if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & (0x01 << i)) break; } nand_onfi_timing_set(denali, i); return PASS; }