void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
nbmc_write_index(nb_dev, reg_pos, reg);
}
}
/*****************************************
* Compliant with CIM_33's ATINB_MiscClockCtrl
*****************************************/
void static rs690_config_misc_clk(device_t nb_dev)
{
u32 reg;
u16 word;
/* u8 byte; */
struct bus pbus; /* fake bus for dev0 fun1 */
reg = pci_read_config32(nb_dev, 0x4c);
reg |= 1 << 0;
pci_write_config32(nb_dev, 0x4c, reg);
word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
word &= 0xf00;
pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
word &= ~((1 << 12) | (1 << 13) | (1 << 14));
word |= 1 << 13;
pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
reg |= 1 << 13;
pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
reg |= 1 << 24;
pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
reg = nbmc_read_index(nb_dev, 0x7a);
reg &= ~0x3f;
reg |= 1 << 2;
reg &= ~(1 << 6);
set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
nbmc_write_index(nb_dev, 0x7a, reg);
/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
reg &= ~(1 << 23);
reg |= 1 << 24;
pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
#if 0
/* Powerdown reference clock to graphics core PLL in northbridge only mode */
reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
reg |= 1 << 21;
pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
reg |= (1 << 23) | (1 << 24);
pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
/* Powerdown clock to memory controller in northbridge only mode */
byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
byte |= 1 << 0;
pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
/* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
/* TODO: */
#endif
reg = pci_read_config32(nb_dev, 0x4c);
reg &= ~(1 << 0);
pci_write_config32(nb_dev, 0x4c, reg);
set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
}
/*
* nb_misc_clock :
* rs690 misc clock parameters setting
*/
static void nb_misc_clock(void)
{
pcitag_t clk_dev = _pci_make_tag(0, 0, 1);
pcitag_t nb_dev = _pci_make_tag(0, 0, 0);
pcitag_t gfx_dev2 = _pci_make_tag(0, 2, 0);
u8 rev = get_nb_revision();
u32 val;
/* visible CLK func */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0);
if(ati_nb_cfg.ext_config & EXT_DEBUG_NB_DYNAMIC_CLK){
/* disable NB dynamic clock to htiu rx */
set_nbcfg_enable_bits(clk_dev, 0xE8, 0x07 << 12, 1 << 13);
/* ENABLE : CLKGATE_DIS_GFX_TXCLK & CLKGATE_DIS_GPPSB_CCLK & CLKGATE_DIS_CFG_S1X */
set_nbcfg_enable_bits(clk_dev, 0x94, (1 << 16) | (1 << 24) | (1 << 28), 0);
/* ENABEL : CLKDATE_DIS_IOC_CCLK_MST/SLV, enabel clkdate for C/MCLK goto BIF branch */
set_nbcfg_enable_bits(clk_dev, 0x8C, (1 << 13) | (1 << 14) | (1 << 24) | (1 << 25), 0);
if(rev < REV_RS690_A21){
/* CKLGATE_DIS_IO_CCLK_MST */
set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 13, 1 << 13);
}
/* Powering Down efuse and strap block clocks in GFX mode as default */
set_nbcfg_enable_bits(clk_dev, 0xCC, 1 << 24, 1 << 24);
/* dynamic clock setting for MC and HTIU */
val = nbmc_read_index(nb_dev, 0x7A);
val &= 0xffffffc0;
val |= 1 << 2;
if(rev >= REV_RS690_A21){
val &= ~(1 << 6);
set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
}
nbmc_write_index(nb_dev, 0x7A, val);
if(ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)){
/* Powering Down efuse and strap block clocks in GFX mode : PWM???*/
set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), 1 << 24);
}else{
/* nb only mode */
/* Powers down reference clock to graphics core PLL */
set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 21, 1 << 21);
/* Powering Down efuse and strap block clocks after boot-up */
set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), (1 << 23) | (1 << 24));
/* powerdown clock to MC */
set_nbcfg_enable_bits(clk_dev, 0xE4, 1 << 0, 1 << 0);
}
if(ati_nb_cfg.pcie_gfx_info == 0){
if(_pci_conf_read(gfx_dev2, 0x00) == 0xffffffff){
/* Powerdown GFX ports clock when no external GFX detected */
set_nbcfg_enable_bits(clk_dev, 0xE8, 1 << 17, 1 << 17);
}
}
}
/* hide CLK func */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 0 << 0);
if(rev >= REV_RS690_A21){
set_htiu_enable_bits(nb_dev, 0x05, (1 << 8) | (1 << 9), (1 << 8) | (1 << 9));
set_htiu_enable_bits(nb_dev, 0x05, (1 << 10), (1 << 10));
}
DEBUG_INFO("NB POST STAGE : nb_misc_clock function : should we use PWM for efuse and strap powerdown?\n");
return;
}
