int main(int argc, char *argv[]) { FILE *binfile; int max_steps = MAX_STEP; y86sim_t *sim; mem_t *saver, *savem; int step = 0; stat_t e = STAT_AOK; if (argc < 2 || argc > 3) usage(argv[0]); /* set max steps */ if (argc > 2) max_steps = atoi(argv[2]); /* load binary file to memory */ if (strcmp(argv[1]+(strlen(argv[1])-4), ".bin")) usage(argv[0]); /* only support *.bin file */ binfile = fopen(argv[1], "rb"); if (!binfile) { err_print("Can't open binary file '%s'", argv[1]); exit(1); } sim = new_y86sim(MEM_SIZE); if (load_binfile(sim->m, binfile) < 0) { err_print("Failed to load binary file '%s'", argv[1]); free_y86sim(sim); exit(1); } fclose(binfile); /* save initial register and memory stat */ saver = dup_reg(sim->r); savem = dup_mem(sim->m); /* execute binary code step-by-step */ for (step = 0; step < max_steps && e == STAT_AOK; step++) e = nexti(sim); /* print final stat of y86sim */ printf("Stopped in %d steps at PC = 0x%x. Status '%s', CC %s\n", step, sim->pc, stat_name(e), cc_name(sim->cc)); printf("Changes to registers:\n"); diff_reg(saver, sim->r, stdout); printf("\nChanges to memory:\n"); diff_mem(savem, sim->m, stdout); free_y86sim(sim); free_reg(saver); free_mem(savem); return 0; }
void IndexedBranchNode::gen() { // generates n-way indexed branch; // fall-through code is non-int or out of bounds BasicNode::gen(); r = genHelper->moveToReg(_src, IndexReg); // check bounds genHelper->loadImmediateOop(as_smiOop(nCases), BoundsReg, true); theAssembler->TSubCCR( BoundsReg, r, G0); Label* end = theAssembler->BleuForward(false); theAssembler->Nop(); // check tag (reuse bounds cmp) if (!srcMustBeSmi) { end->unify( theAssembler->BvsForward(false)); theAssembler->Nop(); } char* cra= theAssembler->addr(); const int32 bytesFromCallToJump = 4 * sizeof(int32); const int32 bytesFromCallToInstAfterDelay = 2 * sizeof(int32); // only on V9: theAssembler.ReadPC(Temp2); theAssembler->CallN( theAssembler->addr() + bytesFromCallToInstAfterDelay); const int32 indexShift = 2 - Tag_Size; assert(indexShift == 0, "no shift needed"); theAssembler->AddR( r, CalleeReturnAddr, BoundsReg); // delay slot assert( theAssembler->addr() - cra == bytesFromCallToInstAfterDelay, "recount instructions"); theAssembler->JmpLI( BoundsReg, bytesFromCallToJump - (Int_Tag << indexShift), G0); theAssembler->Nop(); // delay slot for jmp, cannot have branch here assert( theAssembler->addr() - cra == bytesFromCallToJump, "recount instructions"); for (fint i = 0; i < nCases; ++i) { Label* l_ = theAssembler->BraForward(true); Node* n = nexti(i + 1); n->l = l_->unify(n->l); } end->define(); }
void TBranchNode::testTagsIfNecessary(bool haveImmediate, Location rcvrReg, Location argReg) { // test both tags (overflow might be false alarm) if (SICCountTypeTests) { // not sure if type test counting stuff is right anymore -- dmu theAssembler->startTypeTest(2, false, true); theAssembler->doOneTypeTest(); } if (SICCountIntTagTests) theAssembler->markTagTest(2); Label* noPrimFailure = theAssembler->BvcForward(false); theAssembler->Nop(); Label*& ovflLabel = ((MergeNode*)nexti(2))->l; if (!intRcvr) { theAssembler->TAddCCI(rcvrReg, 0, G0); ovflLabel = ovflLabel->unify(theAssembler->BvsForward(false)); } if (!intArg) { theAssembler->TAddCCI(argReg, 0, G0); ovflLabel = ovflLabel->unify(theAssembler->BvsForward(false)); } if (SICCountTypeTests) theAssembler->endTypeTest(); genCompare(haveImmediate, rcvrReg, argReg); noPrimFailure->define(); // define no non-int destination }