static void nic_init_hw(struct nicpf *nic) { int i; u64 cqm_cfg; /* Enable NIC HW block */ nic_reg_write(nic, NIC_PF_CFG, 0x3); /* Enable backpressure */ nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03); /* TNS and TNS bypass modes are present only on 88xx * Also offset of this CSR has changed in 81xx and 83xx. */ if (nic->pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF) { /* Disable TNS mode on both interfaces */ nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK | (1ULL << 16)); nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK | (1ULL << 16)); } else { /* Configure timestamp generation timeout to 10us */ for (i = 0; i < nic->hw->bgx_cnt; i++) nic_reg_write(nic, NIC_PF_INTFX_SEND_CFG | (i << 3), (1ULL << 16)); } nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, (1ULL << 63) | BGX0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), (1ULL << 63) | BGX1_BLOCK); /* PKIND configuration */ nic->pkind.minlen = 0; nic->pkind.maxlen = NIC_HW_MAX_FRS + VLAN_ETH_HLEN + ETH_FCS_LEN + 4; nic->pkind.lenerr_en = 1; nic->pkind.rx_hdr = 0; nic->pkind.hdr_sl = 0; for (i = 0; i < NIC_MAX_PKIND; i++) nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), *(u64 *)&nic->pkind); nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); /* Timer config */ nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); /* Enable VLAN ethertype matching and stripping */ nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q); /* Check if HW expected value is higher (could be in future chips) */ cqm_cfg = nic_reg_read(nic, NIC_PF_CQM_CFG); if (cqm_cfg < NICPF_CQM_MIN_DROP_LEVEL) nic_reg_write(nic, NIC_PF_CQM_CFG, NICPF_CQM_MIN_DROP_LEVEL); }
static void nic_init_hw(struct nicpf *nic) { int i; u64 cqm_cfg; /* Enable NIC HW block */ nic_reg_write(nic, NIC_PF_CFG, 0x3); /* Enable backpressure */ nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03); /* Disable TNS mode on both interfaces */ nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, (1ULL << 63) | BGX0_BLOCK); nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), (1ULL << 63) | BGX1_BLOCK); /* PKIND configuration */ nic->pkind.minlen = 0; nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN; nic->pkind.lenerr_en = 1; nic->pkind.rx_hdr = 0; nic->pkind.hdr_sl = 0; for (i = 0; i < NIC_MAX_PKIND; i++) nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), *(u64 *)&nic->pkind); nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); /* Timer config */ nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); /* Enable VLAN ethertype matching and stripping */ nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q); /* Check if HW expected value is higher (could be in future chips) */ cqm_cfg = nic_reg_read(nic, NIC_PF_CQM_CFG); if (cqm_cfg < NICPF_CQM_MIN_DROP_LEVEL) nic_reg_write(nic, NIC_PF_CQM_CFG, NICPF_CQM_MIN_DROP_LEVEL); }