void olim24_init()
{
common_init();
keyboard_olim24_init();
nvr_init();
olivetti_m24_init();
xtide_init();
nmi_init();
}
void xt_init()
{
common_init();
pit_set_out_func(1, pit_refresh_timer_xt);
keyboard_xt_init();
mouse_serial_init();
xtide_init();
nmi_init();
}
void europc_init()
{
common_init();
jim_init();
keyboard_xt_init();
mouse_serial_init();
xtide_init();
nmi_init();
}
void ams_init()
{
AMSTRAD = 1;
common_init();
amstrad_init();
keyboard_amstrad_init();
nvr_init();
xtide_init();
nmi_init();
fdc_set_dskchg_activelow();
}
void olim24_init()
{
common_init();
mem_add_bios();
keyboard_olim24_init();
nvr_init();
olivetti_m24_init();
xtide_init();
nmi_init();
device_add(&gameport_device);
}
void xt_init()
{
common_init();
mem_add_bios();
pit_set_out_func(1, pit_refresh_timer_xt);
keyboard_xt_init();
mouse_serial_init();
xtide_init();
nmi_init();
device_add(&gameport_device);
}
void europc_init()
{
common_init();
mem_add_bios();
jim_init();
keyboard_xt_init();
mouse_serial_init();
xtide_init();
nmi_init();
device_add(&gameport_device);
}
void tandy1ksl2_init()
{
// TANDY = 1;
common_init();
keyboard_tandy_init();
mouse_serial_init();
device_add(&pssj_device);
xtide_init();
nmi_init();
device_add(&tandy_rom_device);
device_add(&tandy_eeprom_device);
}
void ams_init()
{
AMSTRAD = 1;
common_init();
mem_add_bios();
amstrad_init();
keyboard_amstrad_init();
nvr_init();
xtide_init();
nmi_init();
fdc_set_dskchg_activelow();
device_add(&gameport_device);
}
void olim24_init()
{
PCI = 0;
maxide = 2;
AT = 0;
is386 = 0;
common_init();
keyboard_olim24_init();
nvr_init();
olivetti_m24_init();
xtide_init();
nmi_init();
}
void europc_init()
{
PCI = 0;
maxide = 2;
AT = 0;
is386 = 0;
common_init();
jim_init();
keyboard_xt_init();
mouse_serial_init();
xtide_init();
nmi_init();
}
void xt_init()
{
PCI = 0;
maxide = 2;
AT = 0;
is386 = 0;
common_init();
pit_set_out_func(1, pit_refresh_timer_xt);
keyboard_xt_init();
mouse_serial_init();
xtide_init();
nmi_init();
}
void tandy1k_init()
{
PCI = 0;
maxide = 2;
AT = 0;
is386 = 0;
common_init();
keyboard_xt_init();
mouse_serial_init();
device_add(&sn76489_device);
xtide_init();
nmi_init();
fdc_polarity_reset();
}
void tandy1k_init()
{
TANDY = 1;
common_init();
keyboard_tandy_init();
mouse_serial_init();
if (romset == ROM_TANDY)
device_add(&sn76489_device);
else
device_add(&ncr8496_device);
xtide_init();
nmi_init();
if (romset != ROM_TANDY)
device_add(&tandy_eeprom_device);
}
void ams_init()
{
PCI = 0;
maxide = 2;
AT = 0;
is386 = 0;
common_init();
amstrad_init();
keyboard_amstrad_init();
nvr_init();
xtide_init();
nmi_init();
machine_class = MC_AMSTRAD;
fdc_set_dskchg_activelow();
}
int __init pcr_arch_init(void)
{
int err = register_perf_hsvc();
if (err)
return err;
switch (tlb_type) {
case hypervisor:
pcr_ops = &n2_pcr_ops;
pcr_enable = PCR_N2_ENABLE;
picl_shift = 2;
break;
case cheetah:
case cheetah_plus:
pcr_ops = &direct_pcr_ops;
pcr_enable = PCR_SUN4U_ENABLE;
break;
case spitfire:
/* UltraSPARC-I/II and derivatives lack a profile
* counter overflow interrupt so we can't make use of
* their hardware currently.
*/
/* fallthrough */
default:
err = -ENODEV;
goto out_unregister;
}
return nmi_init();
out_unregister:
unregister_perf_hsvc();
return err;
}
