void * nv04_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl, u32 id, int khz) { struct nv04_pm_state *state; int ret; state = kzalloc(sizeof(*state), GFP_KERNEL); if (!state) return ERR_PTR(-ENOMEM); ret = get_pll_limits(dev, id, &state->pll); if (ret) { kfree(state); return (ret == -ENOENT) ? NULL : ERR_PTR(ret); } ret = nouveau_calc_pll_mnp(dev, &state->pll, khz, &state->calc); if (!ret) { kfree(state); return ERR_PTR(-EINVAL); } return state; }
static int calc_pll(struct drm_device *dev, u32 id, int khz, struct nv04_pm_clock *clk) { int ret; ret = get_pll_limits(dev, id, &clk->pll); if (ret) return ret; ret = nouveau_calc_pll_mnp(dev, &clk->pll, khz, &clk->calc); if (!ret) return -EINVAL; return 0; }
int nv50_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk, int *N1, int *M1, int *N2, int *M2, int *P) { struct nouveau_pll_vals pll_vals; int ret; ret = nouveau_calc_pll_mnp(dev, pll, clk, &pll_vals); if (ret <= 0) return ret; *N1 = pll_vals.N1; *M1 = pll_vals.M1; *N2 = pll_vals.N2; *M2 = pll_vals.M2; *P = pll_vals.log2P; return ret; }