/*
* AP cpu's call this to sync up protected mode.
*
* WARNING! We must ensure that the cpu is sufficiently initialized to
* be able to use to the FP for our optimized bzero/bcopy code before
* we enter more mainstream C code.
*
* WARNING! %fs is not set up on entry. This routine sets up %fs.
*/
void
init_secondary(void)
{
int gsel_tss;
int x, myid = bootAP;
u_int cr0;
struct mdglobaldata *md;
struct privatespace *ps;
ps = &CPU_prvspace[myid];
gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
gdt_segs[GPROC0_SEL].ssd_base =
(int) &ps->mdglobaldata.gd_common_tss;
ps->mdglobaldata.mi.gd_prvspace = ps;
for (x = 0; x < NGDT; x++) {
ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
}
r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
r_gdt.rd_base = (int) &gdt[myid * NGDT];
lgdt(&r_gdt); /* does magic intra-segment return */
lidt(&r_idt);
lldt(_default_ldt);
mdcpu->gd_currentldt = _default_ldt;
gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
md->gd_common_tssd = *md->gd_tss_gdt;
ltr(gsel_tss);
/*
* Set to a known state:
* Set by mpboot.s: CR0_PG, CR0_PE
* Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
*/
cr0 = rcr0();
cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
load_cr0(cr0);
pmap_set_opt(); /* PSE/4MB pages, etc */
/* set up CPU registers and state */
cpu_setregs();
/* set up FPU state on the AP */
npxinit(__INITIAL_NPXCW__);
/* set up SSE registers */
enable_sse();
}
/*
* The CPU ends up here when it's ready to run
* XXX should share some of this with init386 in machdep.c
* for now it jumps into an infinite loop.
*/
void
cpu_hatch(void *v)
{
struct cpu_info *ci = (struct cpu_info *)v;
int s;
cpu_init_idt();
lapic_enable();
lapic_startclock();
lapic_set_lvt();
gdt_init_cpu(ci);
lldt(0);
npxinit(ci);
cpu_init(ci);
/* Re-initialise memory range handling on AP */
if (mem_range_softc.mr_op != NULL)
mem_range_softc.mr_op->initAP(&mem_range_softc);
s = splhigh(); /* XXX prevent softints from running here.. */
lapic_tpr = 0;
enable_intr();
if (mp_verbose)
printf("%s: CPU at apid %ld running\n",
ci->ci_dev.dv_xname, ci->ci_cpuid);
nanouptime(&ci->ci_schedstate.spc_runtime);
splx(s);
SCHED_LOCK(s);
cpu_switchto(NULL, sched_chooseproc());
}
/*
* AP CPU's call this to initialize themselves.
*/
void
init_secondary(void)
{
vm_offset_t addr;
u_int cpuid;
int gsel_tss;
/* bootAP is set in start_ap() to our ID. */
PCPU_SET(currentldt, _default_ldt);
gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
#if 0
gdt[bootAP * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
#endif
PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
#if 0
PCPU_SET(tss_gdt, &gdt[bootAP * NGDT + GPROC0_SEL].sd);
PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
#endif
PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
/*
* Set to a known state:
* Set by mpboot.s: CR0_PG, CR0_PE
* Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
*/
/*
* signal our startup to the BSP.
*/
mp_naps++;
/* Spin until the BSP releases the AP's. */
while (!aps_ready)
ia32_pause();
/* BSP may have changed PTD while we were waiting */
invltlb();
for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
invlpg(addr);
/* set up FPU state on the AP */
npxinit();
#if 0
/* set up SSE registers */
enable_sse();
#endif
#if 0 && defined(PAE)
/* Enable the PTE no-execute bit. */
if ((amd_feature & AMDID_NX) != 0) {
uint64_t msr;
msr = rdmsr(MSR_EFER) | EFER_NXE;
wrmsr(MSR_EFER, msr);
}
#endif
#if 0
/* A quick check from sanity claus */
if (PCPU_GET(apic_id) != lapic_id()) {
printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
printf("SMP: actual apic_id = %d\n", lapic_id());
printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
panic("cpuid mismatch! boom!!");
}
#endif
/* Initialize curthread. */
KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
PCPU_SET(curthread, PCPU_GET(idlethread));
mtx_lock_spin(&ap_boot_mtx);
#if 0
/* Init local apic for irq's */
lapic_setup(1);
#endif
smp_cpus++;
cpuid = PCPU_GET(cpuid);
CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
printf("SMP: AP CPU #%d Launched!\n", cpuid);
/* Determine if we are a logical CPU. */
if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
CPU_SET(cpuid, &logical_cpus_mask);
/* Determine if we are a hyperthread. */
if (hyperthreading_cpus > 1 &&
PCPU_GET(apic_id) % hyperthreading_cpus != 0)
CPU_SET(cpuid, &hyperthreading_cpus_mask);
#if 0
if (bootverbose)
lapic_dump("AP");
#endif
if (smp_cpus == mp_ncpus) {
/* enable IPI's, tlb shootdown, freezes etc */
atomic_store_rel_int(&smp_started, 1);
smp_active = 1; /* historic */
}
mtx_unlock_spin(&ap_boot_mtx);
/* wait until all the AP's are up */
while (smp_started == 0)
ia32_pause();
PCPU_SET(curthread, PCPU_GET(idlethread));
/* Start per-CPU event timers. */
cpu_initclocks_ap();
/* enter the scheduler */
sched_throw(NULL);
panic("scheduler returned us to %s", __func__);
/* NOTREACHED */
}
/*
* AP cpu's call this to sync up protected mode.
*
* WARNING! %gs is not set up on entry. This routine sets up %gs.
*/
void
init_secondary(void)
{
int gsel_tss;
int x, myid = bootAP;
u_int64_t msr, cr0;
struct mdglobaldata *md;
struct privatespace *ps;
ps = &CPU_prvspace[myid];
gdt_segs[GPROC0_SEL].ssd_base =
(long) &ps->mdglobaldata.gd_common_tss;
ps->mdglobaldata.mi.gd_prvspace = ps;
/* We fill the 32-bit segment descriptors */
for (x = 0; x < NGDT; x++) {
if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
}
/* And now a 64-bit one */
ssdtosyssd(&gdt_segs[GPROC0_SEL],
(struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
r_gdt.rd_base = (long) &gdt[myid * NGDT];
lgdt(&r_gdt); /* does magic intra-segment return */
/* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
wrmsr(MSR_FSBASE, 0); /* User value */
wrmsr(MSR_GSBASE, (u_int64_t)ps);
wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]);
#if 0
lldt(_default_ldt);
mdcpu->gd_currentldt = _default_ldt;
#endif
gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
#if 0 /* JG XXX */
md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
#endif
md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
md->gd_common_tssd = *md->gd_tss_gdt;
/* double fault stack */
md->gd_common_tss.tss_ist1 =
(long)&md->mi.gd_prvspace->idlestack[
sizeof(md->mi.gd_prvspace->idlestack)];
ltr(gsel_tss);
/*
* Set to a known state:
* Set by mpboot.s: CR0_PG, CR0_PE
* Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
*/
cr0 = rcr0();
cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
load_cr0(cr0);
/* Set up the fast syscall stuff */
msr = rdmsr(MSR_EFER) | EFER_SCE;
wrmsr(MSR_EFER, msr);
wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
wrmsr(MSR_STAR, msr);
wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
pmap_set_opt(); /* PSE/4MB pages, etc */
pmap_init_pat(); /* Page Attribute Table */
/* set up CPU registers and state */
cpu_setregs();
/* set up SSE/NX registers */
initializecpu(myid);
/* set up FPU state on the AP */
npxinit(__INITIAL_FPUCW__);
/* disable the APIC, just to be SURE */
lapic->svr &= ~APIC_SVR_ENABLE;
}
/*
* Clear registers on exec
*/
void
exec_setregs(u_long entry, u_long stack, u_long ps_strings)
{
struct thread *td = curthread;
struct lwp *lp = td->td_lwp;
struct trapframe *regs = lp->lwp_md.md_regs;
struct pcb *pcb = lp->lwp_thread->td_pcb;
/* was i386_user_cleanup() in NetBSD */
user_ldt_free(pcb);
bzero((char *)regs, sizeof(struct trapframe));
regs->tf_eip = entry;
regs->tf_esp = stack;
regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
regs->tf_ss = 0;
regs->tf_ds = 0;
regs->tf_es = 0;
regs->tf_fs = 0;
regs->tf_gs = 0;
regs->tf_cs = 0;
/* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
regs->tf_ebx = ps_strings;
/*
* Reset the hardware debug registers if they were in use.
* They won't have any meaning for the newly exec'd process.
*/
if (pcb->pcb_flags & PCB_DBREGS) {
pcb->pcb_dr0 = 0;
pcb->pcb_dr1 = 0;
pcb->pcb_dr2 = 0;
pcb->pcb_dr3 = 0;
pcb->pcb_dr6 = 0;
pcb->pcb_dr7 = 0;
if (pcb == td->td_pcb) {
/*
* Clear the debug registers on the running
* CPU, otherwise they will end up affecting
* the next process we switch to.
*/
reset_dbregs();
}
pcb->pcb_flags &= ~PCB_DBREGS;
}
/*
* Initialize the math emulator (if any) for the current process.
* Actually, just clear the bit that says that the emulator has
* been initialized. Initialization is delayed until the process
* traps to the emulator (if it is done at all) mainly because
* emulators don't provide an entry point for initialization.
*/
pcb->pcb_flags &= ~FP_SOFTFP;
/*
* note: do not set CR0_TS here. npxinit() must do it after clearing
* gd_npxthread. Otherwise a preemptive interrupt thread may panic
* in npxdna().
*/
crit_enter();
#if 0
load_cr0(rcr0() | CR0_MP);
#endif
#if NNPX > 0
/* Initialize the npx (if any) for the current process. */
npxinit();
#endif
crit_exit();
/*
* note: linux emulator needs edx to be 0x0 on entry, which is
* handled in execve simply by setting the 64 bit syscall
* return value to 0.
*/
}
