int nrf24l01p_set_address_width(const nrf24l01p_t *dev, nrf24l01p_aw_t aw)
{
char aw_setup;
nrf24l01p_read_reg(dev, REG_SETUP_AW, &aw_setup);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
switch (aw) {
case NRF24L01P_AW_3BYTE:
aw_setup &= ~(3);
aw_setup |= 1;
break;
case NRF24L01P_AW_4BYTE:
aw_setup &= ~(3);
aw_setup |= 2;
break;
case NRF24L01P_AW_5BYTE:
aw_setup &= ~(3);
aw_setup |= 3;
break;
default:
return -1;
}
return nrf24l01p_write_reg(dev, REG_SETUP_AW, aw_setup);
}
int nrf24l01p_set_channel(const nrf24l01p_t *dev, uint8_t chan)
{
if (chan > 125) {
chan = 125;
}
return nrf24l01p_write_reg(dev, REG_RF_CH, chan);
}
int nrf24l01p_off(const nrf24l01p_t *dev)
{
char read;
int status;
nrf24l01p_read_reg(dev, REG_CONFIG, &read);
status = nrf24l01p_write_reg(dev, REG_CONFIG, (read & ~PWR_UP));
xtimer_usleep(DELAY_CHANGE_PWR_MODE_US);
return status;
}
int nrf24l01p_on(nrf24l01p_t *dev)
{
char read;
int status;
nrf24l01p_read_reg(dev, REG_CONFIG, &read);
status = nrf24l01p_write_reg(dev, REG_CONFIG, (read | PWR_UP));
hwtimer_wait(DELAY_CHANGE_PWR_MODE_US);
return status;
}
int nrf24l01p_set_payload_width(nrf24l01p_t *dev, nrf24l01p_rx_pipe_t pipe, char width)
{
char pipe_pw_address;
switch (pipe) {
case NRF24L01P_PIPE0:
pipe_pw_address = REG_RX_PW_P0;
break;
case NRF24L01P_PIPE1:
pipe_pw_address = REG_RX_PW_P1;
break;
case NRF24L01P_PIPE2:
pipe_pw_address = REG_RX_PW_P2;
break;
case NRF24L01P_PIPE3:
pipe_pw_address = REG_RX_PW_P3;
break;
case NRF24L01P_PIPE4:
pipe_pw_address = REG_RX_PW_P4;
break;
case NRF24L01P_PIPE5:
pipe_pw_address = REG_RX_PW_P5;
break;
default:
return -1;
}
if (width < 0) {
return -1;
}
if (width > 32) {
width = 32;
}
return nrf24l01p_write_reg(dev, pipe_pw_address, width);
}
