static vsf_err_t nuc400swj_init_iap(void)
{
uint32_t reg;
uint8_t verify_buff[sizeof(iap_code)];
if (cm_dp_halt())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "halt nuc400");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_unlock())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "unlock NUC chip");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_fmc_enable())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "enable FMC");
return ERRCODE_FAILURE_OPERATION;
}
// write iap_code
if (adi_memap_write_buf32(NUC400_IAP_BASE, (uint8_t*)iap_code,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap_code to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
// verify iap_code
memset(verify_buff, 0, sizeof(iap_code));
if (adi_memap_read_buf32(NUC400_IAP_BASE, verify_buff,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "read flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
if (memcmp(verify_buff, iap_code, sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "verify flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
// write pc
reg = NUC400_IAP_BASE + 1;
if (cm_write_core_register(CM_COREREG_PC, ®))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "write PC");
return ERRCODE_FAILURE_OPERATION;
}
if (cm_dp_resume())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "run iap");
return ERRCODE_FAILURE_OPERATION;
}
return VSFERR_NONE;
}
static vsf_err_t nuc400swj_init_iap(void)
{
uint32_t reg;
uint8_t verify_buff[sizeof(iap_code)];
uint32_t fuse_data[4];
if (cm_dp_halt())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "halt nuc400");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_unlock())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "unlock NUC chip");
return ERRCODE_FAILURE_OPERATION;
}
if (nuc400swj_fmc_enable())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "enable FMC");
return ERRCODE_FAILURE_OPERATION;
}
chip_protected = false;
if (nuc400swj_isp_run(NUC400_REG_ISPCMD_READ,
NUC400_REG_CFG_BA, (uint32_t *)fuse_data, 4, true))
{
return ERRCODE_FAILURE_OPERATION;
}
if ((fuse_data[0] != 0xFFFFFFFF) || (fuse_data[1] != 0xFFFFFFFF) ||
(fuse_data[2] != 0xFFFFFFFF))
{
uint32_t crc32 = 0;
struct crc_t crc8 = {CRC_BITLEN_8, 0xFF, 0x07};
uint8_t *fuse_byte = (uint8_t *)fuse_data;
uint8_t i;
for (i = 0; i < 4; i++)
{
crc8.result = 0xFF;
crc_calc(&crc8, &fuse_byte[i + 0], 1);
crc_calc(&crc8, &fuse_byte[i + 4], 1);
crc_calc(&crc8, &fuse_byte[i + 8], 1);
crc32 |= crc8.result << (i * 8);
}
if (crc32 == fuse_data[3])
{
// checksum ok, option bytes valid
// check if read protected
if (!(fuse_data[0] & 0x00000002))
{
// read protected
chip_protected = true;
LOG_INFO("chip protected");
return VSFERR_NONE;
}
}
}
// write iap_code
if (adi_memap_write_buf32(NUC400_IAP_BASE, (uint8_t*)iap_code,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "load iap_code to SRAM");
return ERRCODE_FAILURE_OPERATION;
}
// verify iap_code
memset(verify_buff, 0, sizeof(iap_code));
if (adi_memap_read_buf32(NUC400_IAP_BASE, verify_buff,
sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "read flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
if (memcmp(verify_buff, iap_code, sizeof(iap_code)))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "verify flash_loader");
return ERRCODE_FAILURE_OPERATION;
}
// write pc
reg = NUC400_IAP_BASE + 1;
if (cm_write_core_register(CM_COREREG_PC, ®))
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "write PC");
return ERRCODE_FAILURE_OPERATION;
}
if (cm_dp_resume())
{
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "run iap");
return ERRCODE_FAILURE_OPERATION;
}
return VSFERR_NONE;
}
