/**
* @brief Function for hardware initialization
* @param sc software handle to the device
*/
int
oce_hw_init(POCE_SOFTC sc)
{
int rc = 0;
rc = oce_POST(sc);
if (rc)
return rc;
/* create the bootstrap mailbox */
rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0);
if (rc) {
device_printf(sc->dev, "Mailbox alloc failed\n");
return rc;
}
rc = oce_reset_fun(sc);
if (rc)
goto error;
rc = oce_mbox_init(sc);
if (rc)
goto error;
rc = oce_get_fw_version(sc);
if (rc)
goto error;
rc = oce_get_fw_config(sc);
if (rc)
goto error;
sc->macaddr.size_of_struct = 6;
rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
&sc->macaddr);
if (rc)
goto error;
if ((IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) || IS_SH(sc)) {
rc = oce_mbox_check_native_mode(sc);
if (rc)
goto error;
} else
sc->be3_native = 0;
return rc;
error:
oce_dma_free(sc, &sc->bsmbx);
device_printf(sc->dev, "Hardware initialisation failed\n");
return rc;
}
/*
* function to do a soft reset on the device
*
* dev - software handle to the device
*
*/
int
oce_pci_soft_reset(struct oce_dev *dev)
{
pcicfg_soft_reset_t soft_rst;
/* struct mpu_ep_control ep_control; */
/* struct pcicfg_online1 online1; */
clock_t tmo;
clock_t earlier = ddi_get_lbolt();
ASSERT(dev != NULL);
/* issue soft reset */
soft_rst.dw0 = OCE_CFG_READ32(dev, PCICFG_SOFT_RESET);
soft_rst.bits.soft_reset = 0x01;
OCE_CFG_WRITE32(dev, PCICFG_SOFT_RESET, soft_rst.dw0);
/* wait till soft reset bit deasserts */
tmo = drv_usectohz(60000000); /* 1.0min */
do {
if ((ddi_get_lbolt() - earlier) > tmo) {
tmo = 0;
break;
}
soft_rst.dw0 = OCE_CFG_READ32(dev, PCICFG_SOFT_RESET);
if (soft_rst.bits.soft_reset)
drv_usecwait(100);
} while (soft_rst.bits.soft_reset);
if (soft_rst.bits.soft_reset) {
oce_log(dev, CE_WARN, MOD_CONFIG,
"0x%x soft_reset"
"bit asserted[1]. Reset failed",
soft_rst.dw0);
return (DDI_FAILURE);
}
return (oce_POST(dev));
} /* oce_pci_soft_reset */
int
oce_hw_init(struct oce_dev *dev)
{
int ret;
struct mac_address_format mac_addr;
ret = oce_POST(dev);
if (ret != DDI_SUCCESS) {
oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
"!!!HW POST1 FAILED");
/* ADD FM FAULT */
return (DDI_FAILURE);
}
/* create bootstrap mailbox */
dev->bmbx = oce_alloc_dma_buffer(dev,
sizeof (struct oce_bmbx), NULL, DDI_DMA_CONSISTENT);
if (dev->bmbx == NULL) {
oce_log(dev, CE_WARN, MOD_CONFIG,
"Failed to allocate bmbx: size = %u",
(uint32_t)sizeof (struct oce_bmbx));
return (DDI_FAILURE);
}
ret = oce_reset_fun(dev);
if (ret != 0) {
oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
"!!!FUNCTION RESET FAILED");
goto init_fail;
}
/* reset the Endianess of BMBX */
ret = oce_mbox_init(dev);
if (ret != 0) {
oce_log(dev, CE_WARN, MOD_CONFIG,
"Mailbox initialization2 Failed with %d", ret);
goto init_fail;
}
/* read the firmware version */
ret = oce_get_fw_version(dev);
if (ret != 0) {
oce_log(dev, CE_WARN, MOD_CONFIG,
"Firmaware version read failed with %d", ret);
goto init_fail;
}
/* read the fw config */
ret = oce_get_fw_config(dev);
if (ret != 0) {
oce_log(dev, CE_WARN, MOD_CONFIG,
"Firmware configuration read failed with %d", ret);
goto init_fail;
}
/* read the Factory MAC address */
ret = oce_read_mac_addr(dev, 0, 1,
MAC_ADDRESS_TYPE_NETWORK, &mac_addr);
if (ret != 0) {
oce_log(dev, CE_WARN, MOD_CONFIG,
"MAC address read failed with %d", ret);
goto init_fail;
}
bcopy(&mac_addr.mac_addr[0], &dev->mac_addr[0], ETHERADDRL);
return (DDI_SUCCESS);
init_fail:
oce_hw_fini(dev);
return (DDI_FAILURE);
}