int lio_cn6xxx_soft_reset(struct octeon_device *oct)
{
octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF);
dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n");
lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_BIST);
octeon_write_csr64(oct, CN6XXX_SLI_SCRATCH1, 0x1234ULL);
lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST);
lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_RST);
/* make sure that the reset is written before starting timer */
mmiowb();
/* Wait for 10ms as Octeon resets. */
mdelay(100);
if (octeon_read_csr64(oct, CN6XXX_SLI_SCRATCH1) == 0x1234ULL) {
dev_err(&oct->pci_dev->dev, "Soft reset failed\n");
return 1;
}
dev_dbg(&oct->pci_dev->dev, "Reset completed\n");
octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF);
return 0;
}
static void cn23xx_disable_vf_interrupt(struct octeon_device *oct, u8 intr_flag)
{
u32 q_no;
if (intr_flag & OCTEON_OUTPUT_INTR) {
for (q_no = 0; q_no < oct->num_oqs; q_no++) {
/* Write all 1's in INT_LEVEL reg to disable PO_INT */
octeon_write_csr64(
oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
0x3fffffffffffff);
}
}
if (intr_flag & OCTEON_INPUT_INTR) {
for (q_no = 0; q_no < oct->num_oqs; q_no++) {
octeon_write_csr64(
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
(octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) &
~(CN23XX_INTR_CINT_ENB |
CN23XX_PKT_IN_DONE_CNT_MASK)));
}
}
if (intr_flag & OCTEON_MBOX_INTR) {
octeon_write_csr64(
oct, CN23XX_VF_SLI_PKT_MBOX_INT(0),
(octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) &
~CN23XX_INTR_MBOX_ENB));
}
}
static int cn23xx_vf_reset_io_queues(struct octeon_device *oct, u32 num_queues)
{
u32 loop = BUSY_READING_REG_VF_LOOP_COUNT;
int ret_val = 0;
u32 q_no;
u64 d64;
for (q_no = 0; q_no < num_queues; q_no++) {
/* set RST bit to 1. This bit applies to both IQ and OQ */
d64 = octeon_read_csr64(oct,
CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
d64 |= CN23XX_PKT_INPUT_CTL_RST;
octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
d64);
}
/* wait until the RST bit is clear or the RST and QUIET bits are set */
for (q_no = 0; q_no < num_queues; q_no++) {
u64 reg_val = octeon_read_csr64(oct,
CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&
!(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&
loop) {
WRITE_ONCE(reg_val, octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)));
loop--;
}
if (!loop) {
dev_err(&oct->pci_dev->dev,
"clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
q_no);
return -1;
}
WRITE_ONCE(reg_val, READ_ONCE(reg_val) &
~CN23XX_PKT_INPUT_CTL_RST);
octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
READ_ONCE(reg_val));
WRITE_ONCE(reg_val, octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)));
if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {
dev_err(&oct->pci_dev->dev,
"clearing the reset failed for qno: %u\n",
q_no);
ret_val = -1;
}
}
return ret_val;
}
static int cn23xx_vf_setup_global_input_regs(struct octeon_device *oct)
{
struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
struct octeon_instr_queue *iq;
u64 q_no, intr_threshold;
u64 d64;
if (cn23xx_vf_reset_io_queues(oct, oct->sriov_info.rings_per_vf))
return -1;
for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) {
void __iomem *inst_cnt_reg;
octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_DOORBELL(q_no),
0xFFFFFFFF);
iq = oct->instr_queue[q_no];
if (iq)
inst_cnt_reg = iq->inst_cnt_reg;
else
inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr +
CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no);
d64 = octeon_read_csr64(oct,
CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no));
d64 &= 0xEFFFFFFFFFFFFFFFL;
octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
d64);
/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
* the Input Queues
*/
octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
CN23XX_PKT_INPUT_CTL_MASK);
/* set the wmark level to trigger PI_INT */
intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) &
CN23XX_PKT_IN_DONE_WMARK_MASK;
writeq((readq(inst_cnt_reg) &
~(CN23XX_PKT_IN_DONE_WMARK_MASK <<
CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) |
(intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS),
inst_cnt_reg);
}
return 0;
}
static void cn23xx_setup_vf_iq_regs(struct octeon_device *oct, u32 iq_no)
{
struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
u64 pkt_in_done;
/* Write the start of the input queue's ring and its size */
octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(iq_no),
iq->base_addr_dma);
octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count);
/* Remember the doorbell & instruction count register addr
* for this queue
*/
iq->doorbell_reg =
(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_DOORBELL(iq_no);
iq->inst_cnt_reg =
(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq_no);
dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
/* Store the current instruction counter (used in flush_iq
* calculation)
*/
pkt_in_done = readq(iq->inst_cnt_reg);
if (oct->msix_on) {
/* Set CINT_ENB to enable IQ interrupt */
writeq((pkt_in_done | CN23XX_INTR_CINT_ENB),
iq->inst_cnt_reg);
}
iq->reset_instr_cnt = 0;
}
static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct)
{
struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
u64 pktctl, tx_pipe, max_oqs;
pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL);
/* 68XX specific */
max_oqs = CFG_GET_OQ_MAX_Q(CHIP_FIELD(oct, cn6xxx, conf));
tx_pipe = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE);
tx_pipe &= 0xffffffffff00ffffULL; /* clear out NUMP field */
tx_pipe |= max_oqs << 16; /* put max_oqs in NUMP field */
octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe);
if (CFG_GET_IS_SLI_BP_ON(cn68xx->conf))
pktctl |= 0xF;
else
/* Disable per-port backpressure. */
pktctl &= ~0xF;
octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl);
}
static void cn23xx_enable_vf_interrupt(struct octeon_device *oct, u8 intr_flag)
{
struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
u32 q_no, time_threshold;
if (intr_flag & OCTEON_OUTPUT_INTR) {
for (q_no = 0; q_no < oct->num_oqs; q_no++) {
/* Set up interrupt packet and time thresholds
* for all the OQs
*/
time_threshold = cn23xx_vf_get_oq_ticks(
oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
octeon_write_csr64(
oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
(CFG_GET_OQ_INTR_PKT(cn23xx->conf) |
((u64)time_threshold << 32)));
}
}
if (intr_flag & OCTEON_INPUT_INTR) {
for (q_no = 0; q_no < oct->num_oqs; q_no++) {
/* Set CINT_ENB to enable IQ interrupt */
octeon_write_csr64(
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
((octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) &
~CN23XX_PKT_IN_DONE_CNT_MASK) |
CN23XX_INTR_CINT_ENB));
}
}
/* Set queue-0 MBOX_ENB to enable VF mailbox interrupt */
if (intr_flag & OCTEON_MBOX_INTR) {
octeon_write_csr64(
oct, CN23XX_VF_SLI_PKT_MBOX_INT(0),
(octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) |
CN23XX_INTR_MBOX_ENB));
}
}
static int cn23xx_enable_vf_io_queues(struct octeon_device *oct)
{
u32 q_no;
for (q_no = 0; q_no < oct->num_iqs; q_no++) {
u64 reg_val;
/* set the corresponding IQ IS_64B bit */
if (oct->io_qmask.iq64B & BIT_ULL(q_no)) {
reg_val = octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B;
octeon_write_csr64(
oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
}
/* set the corresponding IQ ENB bit */
if (oct->io_qmask.iq & BIT_ULL(q_no)) {
reg_val = octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB;
octeon_write_csr64(
oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
}
}
for (q_no = 0; q_no < oct->num_oqs; q_no++) {
u32 reg_val;
/* set the corresponding OQ ENB bit */
if (oct->io_qmask.oq & BIT_ULL(q_no)) {
reg_val = octeon_read_csr(
oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no));
reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB;
octeon_write_csr(
oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val);
}
}
return 0;
}
static int lio_cn68xx_setup_device_regs(struct octeon_device *oct)
{
lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT);
lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B);
lio_cn6xxx_enable_error_reporting(oct);
lio_cn6xxx_setup_global_input_regs(oct);
lio_cn68xx_setup_pkt_ctl_regs(oct);
lio_cn6xxx_setup_global_output_regs(oct);
/* Default error timeout value should be 0x200000 to avoid host hang
* when reads invalid register
*/
octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL);
return 0;
}
static void cn23xx_setup_vf_oq_regs(struct octeon_device *oct, u32 oq_no)
{
struct octeon_droq *droq = oct->droq[oq_no];
octeon_write_csr64(oct, CN23XX_VF_SLI_OQ_BASE_ADDR64(oq_no),
droq->desc_ring_dma);
octeon_write_csr(oct, CN23XX_VF_SLI_OQ_SIZE(oq_no), droq->max_count);
octeon_write_csr(oct, CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq_no),
(droq->buffer_size | (OCT_RH_SIZE << 16)));
/* Get the mapped address of the pkt_sent and pkts_credit regs */
droq->pkts_sent_reg =
(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_SENT(oq_no);
droq->pkts_credit_reg =
(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq_no);
}
