int of_pci_address_to_resource(struct device_node *dev, int bar, struct resource *r) { const __be32 *addrp; u64 size; unsigned int flags; addrp = of_get_pci_address(dev, bar, &size, &flags); if (addrp == NULL) return -EINVAL; return __of_address_to_resource(dev, addrp, size, flags, NULL, r); }
static void __iomem *offb_map_reg(struct device_node *np, int index, unsigned long offset, unsigned long size) { const u32 *addrp; u64 asize, taddr; unsigned int flags; addrp = of_get_pci_address(np, index, &asize, &flags); if (addrp == NULL) addrp = of_get_address(np, index, &asize, &flags); if (addrp == NULL) return NULL; if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) return NULL; if ((offset + size) > asize) return NULL; taddr = of_translate_address(np, addrp); if (taddr == OF_BAD_ADDR) return NULL; return ioremap(taddr + offset, size); }
static int __init add_legacy_pci_port(struct device_node *np, struct device_node *pci_dev) { u64 addr, base; const u32 *addrp; unsigned int flags; int iotype, index = -1, lindex = 0; DBG(" -> add_legacy_pci_port(%s)\n", np->full_name); /* We only support ports that have a clock frequency properly * encoded in the device-tree (that is have an fcode). Anything * else can't be used that early and will be normally probed by * the generic 8250_pci driver later on. The reason is that 8250 * compatible UARTs on PCI need all sort of quirks (port offsets * etc...) that this code doesn't know about */ if (of_get_property(np, "clock-frequency", NULL) == NULL) return -1; /* Get the PCI address. Assume BAR 0 */ addrp = of_get_pci_address(pci_dev, 0, NULL, &flags); if (addrp == NULL) return -1; /* We only support BAR 0 for now */ iotype = (flags & IORESOURCE_MEM) ? UPIO_MEM : UPIO_PORT; addr = of_translate_address(pci_dev, addrp); if (addr == OF_BAD_ADDR) return -1; /* Set the IO base to the same as the translated address for MMIO, * or to the domain local IO base for PIO (it will be fixed up later) */ if (iotype == UPIO_MEM) base = addr; else base = addrp[2]; /* Try to guess an index... If we have subdevices of the pci dev, * we get to their "reg" property */ if (np != pci_dev) { const u32 *reg = of_get_property(np, "reg", NULL); if (reg && (*reg < 4)) index = lindex = *reg; } /* Local index means it's the Nth port in the PCI chip. Unfortunately * the offset to add here is device specific. We know about those * EXAR ports and we default to the most common case. If your UART * doesn't work for these settings, you'll have to add your own special * cases here */ if (of_device_is_compatible(pci_dev, "pci13a8,152") || of_device_is_compatible(pci_dev, "pci13a8,154") || of_device_is_compatible(pci_dev, "pci13a8,158")) { addr += 0x200 * lindex; base += 0x200 * lindex; } else { addr += 8 * lindex; base += 8 * lindex; } /* Add port, irq will be dealt with later. We passed a translated * IO port value. It will be fixed up later along with the irq */ return add_legacy_port(np, index, iotype, base, addr, NO_IRQ, UPF_BOOT_AUTOCONF, np != pci_dev); }