static int
psci_attach(device_t dev)
{
struct psci_softc *sc = device_get_softc(dev);
const struct ofw_compat_data *ocd;
psci_initfn_t psci_init;
phandle_t node;
if (psci_softc != NULL)
return (ENXIO);
ocd = ofw_bus_search_compatible(dev, compat_data);
psci_init = (psci_initfn_t)ocd->ocd_data;
KASSERT(psci_init != NULL, ("PSCI init function cannot be NULL"));
node = ofw_bus_get_node(dev);
sc->psci_call = psci_get_callfn(node);
if (sc->psci_call == NULL)
return (ENXIO);
if (psci_init(dev))
return (ENXIO);
psci_softc = sc;
return (0);
}
static int
aw_ts_attach(device_t dev)
{
struct aw_ts_softc *sc;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, aw_ts_spec, sc->res) != 0) {
device_printf(dev, "could not allocate memory resource\n");
return (ENXIO);
}
if (bus_setup_intr(dev, sc->res[1],
INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ts_intr, sc,
&sc->intrhand)) {
bus_release_resources(dev, aw_ts_spec, sc->res);
device_printf(dev, "cannot setup interrupt handler\n");
return (ENXIO);
}
/*
* Thoses magic values were taken from linux which take them from
* the allwinner SDK or found them by deduction
*/
switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
case A10_TS:
sc->temp_offset = 257000;
sc->temp_step = 133;
break;
case A13_TS:
sc->temp_offset = 144700;
sc->temp_step = 100;
break;
}
/* Enable clock and set divisers */
WRITE(sc, TP_CTRL0, TP_CTRL0_CLK_SELECT(0) |
TP_CTRL0_CLK_DIV(2) |
TP_CTRL0_FS_DIV(7) |
TP_CTRL0_TACQ(63));
/* Enable TS module */
WRITE(sc, TP_CTRL1, TP_CTRL1_MODE_EN);
/* Enable Temperature, period is ~2s */
WRITE(sc, TP_TPR, TP_TPR_TEMP_EN | TP_TPR_TEMP_PERIOD(1953));
/* Enable temp irq */
WRITE(sc, TP_FIFOC, TP_FIFOC_TEMP_IRQ_ENABLE);
/* Add sysctl */
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD,
&sc->temp_data, 0, sysctl_handle_int,
"IK3", "CPU Temperature");
return (0);
}
static int
uart_fdt_probe(device_t dev)
{
struct uart_softc *sc;
phandle_t node;
pcell_t clock, shift;
int err;
const struct ofw_compat_data * cd;
sc = device_get_softc(dev);
if (!ofw_bus_status_okay(dev))
return (ENXIO);
cd = ofw_bus_search_compatible(dev, compat_data);
if (cd->ocd_data == (uintptr_t)NULL)
return (ENXIO);
sc->sc_class = (struct uart_class *)cd->ocd_data;
node = ofw_bus_get_node(dev);
if ((err = uart_fdt_get_clock(node, &clock)) != 0)
return (err);
uart_fdt_get_shift(node, &shift);
return (uart_bus_probe(dev, (int)shift, (int)clock, 0, 0));
}
static int
aw_sid_attach(device_t dev)
{
struct aw_sid_softc *sc;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, aw_sid_spec, &sc->res) != 0) {
device_printf(dev, "cannot allocate resources for device\n");
return (ENXIO);
}
aw_sid_sc = sc;
sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
switch (sc->type) {
case A83T_SID:
sc->root_key_off = A83T_ROOT_KEY_OFF;
break;
default:
sc->root_key_off = A10_ROOT_KEY_OFF;
break;
}
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "rootkey",
CTLTYPE_STRING | CTLFLAG_RD,
dev, AW_SID_ROOT_KEY, aw_sid_sysctl, "A", "Root Key");
return (0);
}
static int
clk_fixed_attach(device_t dev)
{
struct clk_fixed_softc *sc;
intptr_t clk_type;
phandle_t node;
struct clk_fixed_def def;
int rv;
sc = device_get_softc(dev);
sc->dev = dev;
node = ofw_bus_get_node(dev);
clk_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
bzero(&def, sizeof(def));
if (clk_type == CLK_TYPE_FIXED)
rv = clk_fixed_init_fixed(sc, node, &def);
else if (clk_type == CLK_TYPE_FIXED_FACTOR)
rv = clk_fixed_init_fixed_factor(sc, node, &def);
else
rv = ENXIO;
if (rv != 0) {
device_printf(sc->dev, "Cannot FDT parameters.\n");
goto fail;
}
rv = clk_parse_ofw_clk_name(dev, node, &def.clkdef.name);
if (rv != 0) {
device_printf(sc->dev, "Cannot parse clock name.\n");
goto fail;
}
sc->clkdom = clkdom_create(dev);
KASSERT(sc->clkdom != NULL, ("Clock domain is NULL"));
rv = clknode_fixed_register(sc->clkdom, &def);
if (rv != 0) {
device_printf(sc->dev, "Cannot register fixed clock.\n");
rv = ENXIO;
goto fail;
}
rv = clkdom_finit(sc->clkdom);
if (rv != 0) {
device_printf(sc->dev, "Clk domain finit fails.\n");
rv = ENXIO;
goto fail;
}
#ifdef CLK_DEBUG
clkdom_dump(sc->clkdom);
#endif
OF_prop_free(__DECONST(char *, def.clkdef.name));
OF_prop_free(def.clkdef.parent_names);
return (bus_generic_attach(dev));
fail:
OF_prop_free(__DECONST(char *, def.clkdef.name));
OF_prop_free(def.clkdef.parent_names);
return (rv);
}
static int
tegra_lic_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
return (BUS_PROBE_DEFAULT);
}
static uintptr_t
uart_fdt_find_device(device_t dev)
{
struct ofw_compat_data **cd;
const struct ofw_compat_data *ocd;
SET_FOREACH(cd, uart_fdt_class_and_device_set) {
ocd = ofw_bus_search_compatible(dev, *cd);
if (ocd->ocd_data != 0)
return (ocd->ocd_data);
}
static int
imx_gpt_probe(device_t dev)
{
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
device_set_desc(dev, "Freescale i.MX GPT timer");
return (BUS_PROBE_DEFAULT);
}
return (ENXIO);
}
static int
pl310_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
return (ENXIO);
device_set_desc(dev, "PL310 L2 cache controller");
return (0);
}
static int
arm_gic_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
return (ENXIO);
device_set_desc(dev, "ARM Generic Interrupt Controller");
return (BUS_PROBE_DEFAULT);
}
static int
aw_usbclk_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
device_set_desc(dev, "Allwinner USB Clocks");
return (BUS_PROBE_DEFAULT);
}
