static int ofw_pcib_attach(device_t dev) { struct ofw_pcib_gen_softc *sc; sc = device_get_softc(dev); /* Quirk handling */ switch (pci_get_devid(dev)) { /* * The ALi M5249 found in Fire-based machines by definition must me * subtractive as they have a ISA bridge on their secondary side but * don't indicate this in the class code although the ISA I/O range * isn't included in their bridge decode. */ case 0x524910b9: sc->ops_pcib_sc.flags |= PCIB_SUBTRACTIVE; break; } ofw_pcib_gen_setup(dev); pcib_attach_common(dev); device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); }
static int ofw_pcib_attach(device_t dev) { struct ofw_pcib_gen_softc *sc; sc = device_get_softc(dev); switch (pci_get_devid(dev)) { /* * The ALi M5249 found in Fire-based machines by definition must me * subtractive as they have a ISA bridge on their secondary side but * don't indicate this in the class code although the ISA I/O range * isn't included in their bridge decode. */ case PCI_DEVID_ALI_M5249: sc->ops_pcib_sc.flags |= PCIB_SUBTRACTIVE; break; } switch (pci_get_vendor(dev)) { /* * Concurrently write the primary and secondary bus numbers in order * to work around a bug in PLX PEX 8114 causing the internal shadow * copies of these not to be updated when setting them bytewise. */ case PCI_VENDOR_PLX: pci_write_config(dev, PCIR_PRIBUS_1, pci_read_config(dev, PCIR_SECBUS_1, 1) << 8 | pci_read_config(dev, PCIR_PRIBUS_1, 1), 2); break; } ofw_pcib_gen_setup(dev); pcib_attach_common(dev); return (pcib_attach_child(dev)); }
static int apb_attach(device_t dev) { struct apb_softc *sc; struct sysctl_ctx_list *sctx; struct sysctl_oid *soid; sc = device_get_softc(dev); /* * Get current bridge configuration. */ sc->sc_bsc.ops_pcib_sc.domain = pci_get_domain(dev); sc->sc_bsc.ops_pcib_sc.secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); sc->sc_bsc.ops_pcib_sc.command = pci_read_config(dev, PCIR_COMMAND, 2); sc->sc_bsc.ops_pcib_sc.pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); sc->sc_bsc.ops_pcib_sc.bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); sc->sc_bsc.ops_pcib_sc.bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); sc->sc_bsc.ops_pcib_sc.bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); sc->sc_bsc.ops_pcib_sc.seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); sc->sc_iomap = pci_read_config(dev, APBR_IOMAP, 1); sc->sc_memmap = pci_read_config(dev, APBR_MEMMAP, 1); /* * Setup SYSCTL reporting nodes. */ sctx = device_get_sysctl_ctx(dev); soid = device_get_sysctl_tree(dev); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.domain, 0, "Domain number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.pribus, 0, "Primary bus number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.bus.sec, 0, "Secondary bus number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.bus.sub, 0, "Subordinate bus number"); ofw_pcib_gen_setup(dev); if (bootverbose) { device_printf(dev, " domain %d\n", sc->sc_bsc.ops_pcib_sc.domain); device_printf(dev, " secondary bus %d\n", sc->sc_bsc.ops_pcib_sc.bus.sec); device_printf(dev, " subordinate bus %d\n", sc->sc_bsc.ops_pcib_sc.bus.sub); device_printf(dev, " I/O decode "); apb_map_print(sc->sc_iomap, APB_IO_SCALE); printf("\n"); device_printf(dev, " memory decode "); apb_map_print(sc->sc_memmap, APB_MEM_SCALE); printf("\n"); } device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); }