Exemple #1
0
void __init omap2_map_common_io(void)
{
#if defined(CONFIG_ARCH_OMAP2420)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP2430)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP4)
	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
#endif
	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
	omapfb_reserve_sdram();
	omap_vram_reserve_sdram();
}
Exemple #2
0
void __init omap2_map_common_io(void)
{
#if defined(CONFIG_ARCH_OMAP2420)
    iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
    iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP2430)
    iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
    iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
    iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP4)
    iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
#endif

    local_flush_tlb_all();
    flush_cache_all();

    omap2_check_revision();
    omap_sram_init();
    omapfb_reserve_sdram();
}
static void __init _omap2_map_common_io(void)
{
	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
}
Exemple #4
0
void __init omap2_map_common_io(void)
{
	iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc));

	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
	omapfb_reserve_sdram();
}
Exemple #5
0
static void __init _omap2_map_common_io(void)
{
	omap_l2cache_enable();

	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
	omapfb_reserve_sdram();
	omap_vram_reserve_sdram();
	dspbridge_reserve_sdram();
}
static void __init _omap2_map_common_io(void)
{
	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
	omapfb_reserve_sdram();
	omap_vram_reserve_sdram();
	dspbridge_reserve_sdram();

#ifdef CONFIG_TF_MSHIELD
	tf_allocate_workspace();
#endif
}
Exemple #7
0
static void __init omap_common_init_early(void)
{
	omap2_check_revision();
	omap_ioremap_init();
	omap_init_consistent_dma_size();
}