/* Resets clock rates and reboots the system. Only called from system.h */ void omap_prcm_arch_reset(char mode, const char *cmd) { s16 prcm_offs = 0; if (cpu_is_omap24xx()) { omap2xxx_clk_prepare_for_reboot(); prcm_offs = WKUP_MOD; } else if (cpu_is_omap34xx()) { prcm_offs = OMAP3430_GR_MOD; omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); } else if (cpu_is_omap44xx()) { omap4_prm_global_warm_sw_reset(); /* never returns */ } else if (cpu_is_ti81xx()) { omap2_prm_set_mod_reg_bits(TI81XX_GLOBAL_RST_COLD, prcm_offs, TI81XX_PRM_DEVICE_RSTCTRL); } else { WARN_ON(1); } /* Ensure the sleep script doesn't run */ twl4030_remove_script(TWL4030_SLEEP_SCRIPT); omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL); omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ }
/* Resets clock rates and reboots the system. Only called from system.h */ void omap_prcm_arch_reset(char mode, const char *cmd) { s16 prcm_offs = 0; if (cpu_is_omap24xx()) { omap2xxx_clk_prepare_for_reboot(); prcm_offs = WKUP_MOD; } else if (cpu_is_omap34xx()) { prcm_offs = OMAP3430_GR_MOD; omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); } else if (cpu_is_omap44xx()) { omap4_prm_global_warm_sw_reset(); /* never returns */ } else { WARN_ON(1); } /* * As per Errata i520, in some cases, user will not be able to * access DDR memory after warm-reset. * This situation occurs while the warm-reset happens during a read * access to DDR memory. In that particular condition, DDR memory * does not respond to a corrupted read command due to the warm * reset occurrence but SDRC is waiting for read completion. * SDRC is not sensitive to the warm reset, but the interconnect is * reset on the fly, thus causing a misalignment between SDRC logic, * interconnect logic and DDR memory state. * WORKAROUND: * Steps to perform before a Warm reset is trigged: * 1. enable self-refresh on idle request * 2. put SDRC in idle * 3. wait until SDRC goes to idle * 4. generate SW reset (Global SW reset) * * Steps to be performed after warm reset occurs (in bootloader): * if HW warm reset is the source, apply below steps before any * accesses to SDRAM: * 1. Reset SMS and SDRC and wait till reset is complete * 2. Re-initialize SMS, SDRC and memory * * NOTE: Above work around is required only if arch reset is implemented * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need * the WA since it resets SDRC as well as part of cold reset. */ /* XXX should be moved to some OMAP2/3 specific code */ omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL); omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ }