void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } for (; controllers->mmc; controllers++) omap_init_hsmmc(controllers, controllers->mmc); }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } // from GB MMC0 and MMC1 was swapping. [START] #ifdef TI_FS_MMC for (; controllers->mmc; controllers++) omap_init_hsmmc(controllers, controllers->mmc); #else omap_init_hsmmc(&controllers[1], controllers[1].mmc); omap_init_hsmmc(&controllers[0], controllers[0].mmc); omap_init_hsmmc(&controllers[2], controllers[2].mmc); #endif // TI_FS_MMC // from GB MMC0 and MMC1 was swapping. [END] sd_ldo_init(); }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } if (machine_is_omap3_pandora()) { /* needed for gpio_126 - gpio_129 to work correctly */ reg = omap_ctrl_readl(control_pbias_offset); reg &= ~OMAP343X_PBIASLITEVMODE1; omap_ctrl_writel(reg, control_pbias_offset); } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } for (; controllers->mmc; controllers++) omap_init_hsmmc(controllers, controllers->mmc); }