/** * omap4_opp_init() - initialize omap4 opp table */ int __init omap4_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap44xx()) return r; if (cpu_is_omap443x()) r = omap_init_opp_table(omap443x_opp_def_list, ARRAY_SIZE(omap443x_opp_def_list)); else if (cpu_is_omap446x()) r = omap_init_opp_table(omap446x_opp_def_list, ARRAY_SIZE(omap446x_opp_def_list)); if (!r) { if (omap4_has_mpu_1_2ghz()) omap4_mpu_opp_enable(1200000000); /* 1.8Ghz까지 오버클럭 */ if (omap4_has_mpu_1_5ghz()) omap4_mpu_opp_enable(1340000000); omap4_mpu_opp_enable(1520000000); omap4_mpu_opp_enable(1650000000); } return r; }
/** * omap4_opp_init() - initialize omap4 opp table */ int __init omap4_opp_init(void) { int r = -ENODEV; int trimmed = 1; if (!cpu_is_omap44xx()) return r; if (cpu_is_omap443x()) r = omap_init_opp_table(omap443x_opp_def_list, ARRAY_SIZE(omap443x_opp_def_list)); else if (cpu_is_omap446x()) { r = omap_init_opp_table(omap446x_opp_def_list, ARRAY_SIZE(omap446x_opp_def_list)); trimmed = omap_readl(0x4a002268) & ((1 << 18) | (1 << 19)); /* if device is untrimmed override DPLL TRIM register */ if (!trimmed) omap_writel(0x29, 0x4a002330); } if (!r) { if (omap4_has_mpu_1_2ghz()) omap4_mpu_opp_enable(1200000000); if (!trimmed) pr_info("This is DPLL un-trimmed SOM. OPP is limited at 1.2 GHz\n"); if (omap4_has_mpu_1_5ghz() && trimmed) omap4_mpu_opp_enable(1500000000); } return r; }
/** * omap3_opp_init() - initialize omap3 opp table */ int __init omap3_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap34xx()) return r; if (cpu_is_omap3630()) r = omap_init_opp_table(omap36xx_opp_def_list, ARRAY_SIZE(omap36xx_opp_def_list)); else if (cpu_is_am33xx()) { /* Modified by MYIR */ if (omap_rev() != AM335X_REV_ES1_0) { r = omap_init_opp_table(am33xx_es2x_opp_def_list, ARRAY_SIZE(am33xx_es2x_opp_def_list)); } else { r = omap_init_opp_table(am33xx_opp_def_list, ARRAY_SIZE(am33xx_opp_def_list)); } } else r = omap_init_opp_table(omap34xx_opp_def_list, ARRAY_SIZE(omap34xx_opp_def_list)); return r; }
/** * omap3_opp_init() - initialize omap3 opp table */ int __init omap3_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap34xx()) return r; if (cpu_is_omap3630()) r = omap_init_opp_table(omap36xx_opp_def_list, ARRAY_SIZE(omap36xx_opp_def_list)); else r = omap_init_opp_table(omap34xx_opp_def_list, ARRAY_SIZE(omap34xx_opp_def_list)); return r; }
/** * omap4_opp_init() - initialize omap4 opp table */ static int __init omap5_opp_init(void) { int r = -ENODEV; pr_info("Registering %d OPPs\n", ARRAY_SIZE(omap54xx_opp_def_list)); if (!cpu_is_omap54xx()) return r; r = omap_init_opp_table(omap54xx_opp_def_list, ARRAY_SIZE(omap54xx_opp_def_list)); if (!cpu_is_omap5432()) { /* Enable scaling on the Core domain */ struct omap_hwmod *oh_mpu = omap_hwmod_lookup("l3_main_1"); struct platform_device *pdev; if (!oh_mpu || !oh_mpu->od) { return r; } else { pdev = oh_mpu->od->pdev; r = opp_enable(&pdev->dev, 133000000); if (r < 0) { dev_err(&pdev->dev, "unable to enable Core LOW OPP for 5430 device!\n"); return r; } } pr_info("Added LOW OPP to CORE domain - this is expected on 5430 device\n"); } else { pr_info("Did not LOW OPP to CORE domain - this is expected on 5432 device\n"); } return r; }
/** * omap3_opp_init() - initialize omap3 opp table */ int __init omap3_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap34xx()) return r; if (cpu_is_omap3630()) r = omap_init_opp_table(omap36xx_opp_def_list, ARRAY_SIZE(omap36xx_opp_def_list)); else { r = omap_init_opp_table(omap34xx_opp_def_list, ARRAY_SIZE(omap34xx_opp_def_list)); // if (omap3_has_720mhz()) // r = omap3_opp_enable_720Mhz(); } return r; }
/** * omap3_opp_init() - initialize omap3 opp table */ int __init omap3_opp_init(void) { int r = -ENODEV; memset(omap36xx_opp_def_list_shared, 0, sizeof(omap36xx_opp_def_list_shared)); memcpy(omap36xx_opp_def_list_shared, omap36xx_opp_def_list, sizeof(omap36xx_opp_def_list)); if (!cpu_is_omap34xx()) return r; if (cpu_is_omap3630()) r = omap_init_opp_table(omap36xx_opp_def_list, ARRAY_SIZE(omap36xx_opp_def_list)); else r = omap_init_opp_table(omap34xx_opp_def_list, ARRAY_SIZE(omap34xx_opp_def_list)); return r; }
/** * omap4_opp_init() - initialize omap4 opp table */ int __init omap4_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap44xx()) return r; r = omap_init_opp_table(omap44xx_opp_def_list, ARRAY_SIZE(omap44xx_opp_def_list)); return r; }
/** * omap4_opp_init() - initialize omap4 opp table */ int __init omap4_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap44xx()) return r; if (cpu_is_omap443x()) r = omap_init_opp_table(omap443x_opp_def_list, ARRAY_SIZE(omap443x_opp_def_list)); else if (cpu_is_omap446x()) r = omap_init_opp_table(omap446x_opp_def_list, ARRAY_SIZE(omap446x_opp_def_list)); if (!r) { omap4_opp_enable("mpu", 1200000000); omap4_opp_enable("mpu", 1350000000); omap4_opp_enable("mpu", 1520000000); omap4_opp_enable("mpu", 1650000000); } return r; }
/** * omap4_opp_init() - initialize omap4 opp table */ int __init omap4_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap44xx()) return r; if (cpu_is_omap443x()) r = omap_init_opp_table(omap443x_opp_def_list, ARRAY_SIZE(omap443x_opp_def_list)); else if (cpu_is_omap446x()) r = omap_init_opp_table(omap446x_opp_def_list, ARRAY_SIZE(omap446x_opp_def_list)); if (!r) { if (omap4_has_mpu_1_2ghz()) omap4_mpu_opp_enable(1200000000); omap4_mpu_opp_enable(1350000000); /* The tuna PCB doesn't support 1.5GHz, so disable it for now */ /*if (omap4_has_mpu_1_5ghz()) omap4_mpu_opp_enable(1500000000);*/ } return r; }
/** * omap4_opp_init() - initialize omap4 opp table */ int __init omap4_opp_init(void) { int r = -ENODEV; if (!cpu_is_omap44xx()) return r; if (cpu_is_omap443x()) r = omap_init_opp_table(omap443x_opp_def_list, ARRAY_SIZE(omap443x_opp_def_list)); else if (cpu_is_omap446x()) r = omap_init_opp_table(omap446x_opp_def_list, ARRAY_SIZE(omap446x_opp_def_list)); if (!r) { if (omap4_has_mpu_1_2ghz()) omap4_mpu_opp_enable(1200000000); /* The tuna supports 1.35GHz & 1.42GHz */ if (omap4_has_mpu_1_5ghz()) omap4_mpu_opp_enable(1350000000); omap4_mpu_opp_enable(1420000000); } return r; }