static int imx072_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); struct isp_csi2_lanes_cfg lanecfg; struct isp_csi2_phy_cfg phyconfig; static enum v4l2_power previous_power = V4L2_POWER_OFF; int err = 0; switch (power) { case V4L2_POWER_ON: /* Power Up Sequence */ printk(KERN_DEBUG "imx072_sensor_power_set(ON)\n"); /* * Through-put requirement: * Set max OCP freq for 3630 is 200 MHz through-put * is in KByte/s so 200000 KHz * 4 = 800000 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 800000); /* S[, 20120922, [email protected], PM from froyo. */ doing_wakeup = 1; /* E], 20120922, [email protected], PM from froyo. */ /* Hold a constraint to keep MPU in C1 */ //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2012.05.22] - CAM pm_qos_update_request(&pm_qos_handler, SET_MPU_CONSTRAINT); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2012.05.22] - CAM isp_csi2_reset(&isp->isp_csi2); lanecfg.clk.pol = IMX072_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = IMX072_CSI2_CLOCK_LANE; lanecfg.data[0].pol = IMX072_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = IMX072_CSI2_DATA0_LANE; lanecfg.data[1].pol = IMX072_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = IMX072_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0; lanecfg.data[2].pos = 0; lanecfg.data[3].pol = 0; lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg); isp_csi2_complexio_lanes_update(&isp->isp_csi2, true); isp_csi2_ctrl_config_ecc_enable(&isp->isp_csi2, true); phyconfig.ths_term = IMX072_CSI2_PHY_THS_TERM; phyconfig.ths_settle = IMX072_CSI2_PHY_THS_SETTLE; phyconfig.tclk_term = IMX072_CSI2_PHY_TCLK_TERM; phyconfig.tclk_miss = IMX072_CSI2_PHY_TCLK_MISS; phyconfig.tclk_settle = IMX072_CSI2_PHY_TCLK_SETTLE; isp_csi2_phy_config(&isp->isp_csi2, &phyconfig); isp_csi2_phy_update(&isp->isp_csi2, true); isp_configure_interface(vdev->cam->isp, &imx072_if_config); /* Request and configure gpio pins */ if (gpio_request(IMX072_RESET_GPIO, "imx072_rst") != 0) return -EIO; //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM //KJK for HDMI Sub PMIC usage 2011.03.10 //extern void lp8720_reinit(); //lp8720_reinit(); //gpio_direction_output(lp8720_pdata.en_gpio_num, 1); //subpm_lp8720_power_on(); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM subpm_set_output(SWREG,1); subpm_output_enable(); subpm_set_output(LDO4,1); subpm_output_enable(); subpm_set_output(LDO3,1); subpm_output_enable(); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_1_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); udelay(100); /* have to put sensor to reset to guarantee detection */ gpio_direction_output(IMX072_RESET_GPIO, 1); // gpio_set_value(IMX072_RESET_GPIO, 1); udelay(100); // gpio_direction_output(IMX072_RESET_GPIO, 0); gpio_set_value(IMX072_RESET_GPIO, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ // gpio_direction_output(IMX072_RESET_GPIO, 1); gpio_set_value(IMX072_RESET_GPIO, 1); udelay(300); break; case V4L2_POWER_OFF: //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM printk(KERN_DEBUG "imx072_sensor_power_set(OFF)\n"); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM subpm_set_output(LDO5,0); subpm_output_enable(); //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM //KJK for HDMI Sub PMIC usage 2011.03.10 //gpio_direction_output(lp8720_pdata.en_gpio_num, 0); //subpm_lp8720_power_off(); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM gpio_set_value(DW9716_VCM_ENABLE, 0); //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM /* This is not required cuz it is disabled in isp_csi_memvs.c*/ /* isp_disable_mclk(isp); */ //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); isp_csi2_reset(&isp->isp_csi2); isp_csi2_ctrl_config_ecc_enable(&isp->isp_csi2, true); isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); break; case V4L2_POWER_STANDBY: //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM #ifdef CONFIG_OMAP2_DSS_HDMI { extern int hdmi_power_initialize; int hdmi_wait_cnt = 0; for(hdmi_wait_cnt = 0; hdmi_wait_cnt<20; hdmi_wait_cnt++) { if (hdmi_power_initialize== 0) { printk("==========================================================\n"); printk("waiting DONE for HDMI : %d looping \n", hdmi_wait_cnt); printk("==========================================================\n"); break; } printk("==========================================================\n"); printk("HDMI is not done yet...waiting for HDMI DONE : %d looping \n", hdmi_wait_cnt); printk("==========================================================\n"); msleep(100); } } #endif //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM printk(KERN_DEBUG "imx072_sensor_power_set(%s)\n", (power == V4L2_POWER_OFF) ? "OFF" : "STANDBY"); /* Power Down Sequence */ isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); gpio_set_value(IMX072_RESET_GPIO, 0); udelay(5); subpm_set_output(LDO3,0); subpm_output_enable(); subpm_set_output(LDO4,0); subpm_output_enable(); subpm_set_output(SWREG,0); subpm_output_enable(); gpio_free(IMX072_RESET_GPIO); /* S[, 20120922, [email protected], PM from froyo. */ doing_wakeup = 0; /* E], 20120922, [email protected], PM from froyo. */ /* Remove pm constraints */ //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2012.05.22] - CAM omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, -1); pm_qos_update_request(&pm_qos_handler, CLEAR_MPU_CONSTRAINT); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2012.05.22] - CAM break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
static int mt9v113_sensor_power_set(struct v4l2_int_device *dev, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = dev->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); static enum v4l2_power previous_power = V4L2_POWER_OFF; int err = 0; struct mt9v113_sensor *sensor = dev->priv; switch (power) { case V4L2_POWER_ON: /* Power Up Sequence */ printk(KERN_DEBUG "mt9v113_sensor_power_set(ON)\n"); /* * Through-put requirement: * Set max OCP freq for 3630 is 200 MHz through-put * is in KByte/s so 200000 KHz * 4 = 800000 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 800000); /* S[, 20120922, [email protected], PM from froyo. */ doing_wakeup = 1; /* E], 20120922, [email protected], PM from froyo. */ /* Hold a constraint to keep MPU in C1 */ //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2012.05.22] - CAM pm_qos_update_request(&pm_qos_handler, SET_MPU_CONSTRAINT); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2012.05.22] - CAM isp_configure_interface(vdev->cam->isp,&mt9v113_if_config); if (gpio_request(MT9V113_RESET_GPIO, "mt9v113_rst") != 0) printk("\n\n\n>>>>>>>>>>>>MT9V113_RESET_GPIO_gpio_request_error\n\n\n");//return -EIO; if (gpio_request(MT9V113_STANDBY_GPIO, "mt9v113_PWD") != 0) printk("\n\n\n>>>>>>>>>>>>MT9V113_STANDBY_GPIO_gpio_request_error\n\n\n");//return -EIO;return -EIO; //RESET & PWDN HI gpio_direction_output(MT9V113_RESET_GPIO, true); gpio_set_value(MT9V113_RESET_GPIO, 1); gpio_direction_output(MT9V113_STANDBY_GPIO, true); gpio_set_value(MT9V113_STANDBY_GPIO, 1); mdelay(5); //<1.POWER ON> twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, SET_VMMC1_V2_8,VMMC1_DEDICATED ); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VMMC1_DEV_GRP_P1,VMMC1_DEV_GRP ); //udelay(20); udelay(1); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX3_1_8_V, TWL4030_VAUX3_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX3_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_1_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); mdelay(10); //<2.VGA MCLK ON> //mt9v113_sensor_set_xclk(dev,24000000); //KJK 1211 //sensor->pdata->set_xclk(dev, xclk_current); //sensor->pdata->set_xclk((struct v4l2_int_device *)dev, 24000000); //mdelay(5); //<3.POWER DOWN LOW> //gpio_direction_output(MT9V113_STANDBY_GPIO, true); gpio_set_value(MT9V113_STANDBY_GPIO, 0); mdelay(5); //udelay(2); //<4.RESET> //gpio_set_value(MT9V113_RESET_GPIO, 0); /* set to output mode */ //gpio_direction_output(MT9V113_RESET_GPIO, true); //reset is active low //gpio_set_value(MT9V113_RESET_GPIO, 1); //mdelay(5); gpio_set_value(MT9V113_RESET_GPIO, 0); mdelay(10); gpio_set_value(MT9V113_RESET_GPIO, 1); mdelay(10); break; case V4L2_POWER_OFF: case V4L2_POWER_STANDBY: printk(KERN_DEBUG "mt9v113_sensor_power_set(STANDBY OR OFF) POWER %d\n",power); /* Power Down Sequence */ //<1.POWER DOWN LOW && RESET LOW> gpio_set_value(MT9V113_STANDBY_GPIO, 0); gpio_set_value(MT9V113_RESET_GPIO, 0); mdelay(5); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE,VMMC1_DEV_GRP ); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX3_DEV_GRP); /* twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE,VMMC1_DEV_GRP ); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX3_DEV_GRP); */ mdelay(10); gpio_free(MT9V113_STANDBY_GPIO); gpio_free(MT9V113_RESET_GPIO); /* S[, 20120922, [email protected], PM from froyo. */ doing_wakeup = 0; /* E], 20120922, [email protected], PM from froyo. */ /* Remove pm constraints */ //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2012.05.22] - CAM omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, -1); pm_qos_update_request(&pm_qos_handler, CLEAR_MPU_CONSTRAINT); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2012.05.22] - CAM break; /* case V4L2_POWER_STANDBY: printk(KERN_DEBUG "mt9v113_sensor_power_set(STANDBY)\n"); gpio_free(MT9V113_STANDBY_GPIO); gpio_free(MT9V113_RESET_GPIO); gpio_set_value(MT9V113_STANDBY_GPIO, 0); break; */ } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
static int yacd5b1s_sensor_power_set(struct v4l2_int_device *dev, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = dev->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); static enum v4l2_power previous_power = V4L2_POWER_OFF; //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] static struct pm_qos_request_list *qos_request; // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM int err = 0; switch (power) { case V4L2_POWER_ON: /* Power Up Sequence */ printk(KERN_DEBUG "yacd5b1s_sensor_power_set(ON)\n"); omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 800000); /* Hold a constraint to keep MPU in C1 */ //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] //omap_pm_set_max_mpu_wakeup_lat(vdev->cam->isp, 12); omap_pm_set_max_mpu_wakeup_lat(&qos_request, 12); // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM isp_configure_interface(vdev->cam->isp,&yacd5b1s_if_config); if (gpio_request(YACD5B1S_RESET_GPIO, "yacd5b1s_rst") != 0) printk("\n\n\n>>>>>>>>>>>>YACD5B1S_RESET_GPIO_gpio_request_error\n\n\n");//return -EIO; if (gpio_request(YACD5B1S_STANDBY_GPIO, "yacd5b1s_PWD") != 0) printk("\n\n\n>>>>>>>>>>>>YACD5B1S_STANDBY_GPIO_gpio_request_error\n\n\n");//return -EIO;return -EIO; #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, SET_VMMC1_V2_8,VMMC1_DEDICATED ); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VMMC1_DEV_GRP_P1,VMMC1_DEV_GRP ); #endif udelay(20); #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX3_1_8_V, TWL4030_VAUX3_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX3_DEV_GRP); #endif twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_1_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); //wait typical 500ms for xclk to settle //mdelay(500); gpio_direction_output(YACD5B1S_STANDBY_GPIO, true); udelay(100); gpio_set_value(YACD5B1S_STANDBY_GPIO, 0); udelay(1500); gpio_set_value(YACD5B1S_STANDBY_GPIO, 1); mdelay(100); udelay(50); gpio_direction_output(YACD5B1S_RESET_GPIO, true); udelay(100); gpio_set_value(YACD5B1S_RESET_GPIO, 0); /* set to output mode */ udelay(1500); gpio_set_value(YACD5B1S_RESET_GPIO, 1); udelay(300); break; case V4L2_POWER_OFF: printk(KERN_DEBUG "yacd5b1s_sensor_power_set(OFF)\n"); /* Power Down Sequence */ gpio_set_value(YACD5B1S_RESET_GPIO, 0); udelay(50); gpio_set_value(YACD5B1S_STANDBY_GPIO, 0); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE,VMMC1_DEV_GRP ); #endif #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX3_DEV_GRP); #endif gpio_free(YACD5B1S_STANDBY_GPIO); gpio_free(YACD5B1S_RESET_GPIO); omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, -1); //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] //omap_pm_set_max_mpu_wakeup_lat(vdev->cam->isp, -1); omap_pm_set_max_mpu_wakeup_lat(&qos_request, -1); // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM if (previous_power == V4L2_POWER_ON){ isp_disable_mclk(isp); udelay(5); } break; case V4L2_POWER_STANDBY: printk(KERN_DEBUG "yacd5b1s_sensor_power_set(STANDBY)\n"); gpio_set_value(YACD5B1S_RESET_GPIO, 0); udelay(50); gpio_set_value(YACD5B1S_STANDBY_GPIO, 0); udelay(50); gpio_free(YACD5B1S_STANDBY_GPIO); gpio_free(YACD5B1S_RESET_GPIO); if (previous_power == V4L2_POWER_ON){ isp_disable_mclk(isp); udelay(5); } break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
static int prev2resz_ioc_run_engine(struct prev2resz_fhdl *fh) { struct isp_freq_devider *fdiv; int rval; rval = isppreview_s_pipeline(fh->isp_prev, &fh->prev); if (rval != 0) return rval; rval = isppreview_set_inaddr(fh->isp_prev, fh->src_buff_addr); if (rval != 0) return rval; rval = isppreview_config_inlineoffset(fh->isp_prev, fh->prev.in.image.bytesperline); if (rval != 0) return rval; rval = isppreview_set_outaddr(fh->isp_prev, fh->dst_buff_addr); if (rval != 0) return rval; rval = isppreview_config_features(fh->isp_prev, &fh->isp_prev->params); if (rval != 0) return rval; isppreview_set_size(fh->isp_prev, fh->prev.in.image.width, fh->prev.in.image.height); /* Set resizer input and output size */ rval = ispresizer_s_pipeline(fh->isp_resz, &fh->resz); if (rval != 0) return rval; rval = ispresizer_set_outaddr(fh->isp_resz, fh->dst_buff_addr); if (rval != 0) return rval; isp_configure_interface(fh->isp, &p2r_interface); /* * Through-put requirement: * Set max OCP freq for 3630 is 200 MHz through-put * is in KByte/s so 200000 KHz * 4 = 800000 KByte/s */ omap_pm_set_min_bus_tput(fh->isp, OCP_INITIATOR_AGENT, 800000); /* Reduces memory bandwidth */ fdiv = isp_get_upscale_ratio(fh->pipe.in.image.width, fh->pipe.in.image.height, fh->pipe.out.image.width, fh->pipe.out.image.height); dev_dbg(p2r_device, "Set the REQ_EXP register = %d.\n", fdiv->prev_exp); isp_reg_and_or(fh->isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP, ~(ISPSBL_SDR_REQ_PRV_EXP_MASK | ISPSBL_SDR_REQ_RSZ_EXP_MASK), fdiv->prev_exp << ISPSBL_SDR_REQ_PRV_EXP_SHIFT); isp_start(fh->isp); init_completion(&p2r_ctx.resz_complete); rval = isp_set_callback(fh->isp, CBK_RESZ_DONE, prev2resz_resz_callback, (void *) NULL, (void *) NULL); if (rval) { dev_err(p2r_device, "%s: setting resizer callback failed\n", __func__); return rval; } ispresizer_enable(fh->isp_resz, 1); isppreview_enable(fh->isp_prev, 1); rval = wait_for_completion_interruptible_timeout( &p2r_ctx.resz_complete, msecs_to_jiffies(1000)); if (rval == 0) dev_crit(p2r_device, "Resizer interrupt timeout exit\n"); isp_unset_callback(fh->isp, CBK_RESZ_DONE); /* Reset Through-put requirement */ omap_pm_set_min_bus_tput(fh->isp, OCP_INITIATOR_AGENT, -1); /* This will flushes the queue */ if (&fh->src_vbq) videobuf_queue_cancel(&fh->src_vbq); if (&fh->dst_vbq) videobuf_queue_cancel(&fh->dst_vbq); return 0; }
static void omap3_evm_disable_tv(struct omap_dss_device *dssdev) { omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 0); }
static int gc2015_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); static enum v4l2_power previous_power = V4L2_POWER_OFF; static struct pm_qos_request_list *qos_request; int err = 0; printk(KERN_INFO "previous_power = %d,gc2015_sensor_power_set(%d)\n",previous_power,power); switch (power) { case V4L2_POWER_ON: /* Through-put requirement: * 3280 x 2464 x 2Bpp x 7.5fps x 3 memory ops = 355163 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 664000); /* Hold a constraint to keep MPU in C1 */ omap_pm_set_max_mpu_wakeup_lat(&qos_request, 12); isp_configure_interface(vdev->cam->isp,&gc2015_if_config); udelay(20); //#ifndef KUNLUN_P0 jhy close according to cam poweron timing //gpio_direction_output(GC2015_STANDBY_GPIO, 0); //udelay(10); //#endif // gpio_direction_output(GC2015_RESET_GPIO, 0); /* turn on analog & IO power jhy add VAUX3 Ctrl 2011.6.30*/ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX3_1_8_V, TWL4030_VAUX3_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX3_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX2_1_5_V, TWL4030_VAUX2_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX2_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_2_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); udelay(100); printk(KERN_INFO "VAUX4 = 2.8V\n"); /*jhy add according to cam poweron timing beg 2011.6.30*/ #if 1 /*defined CONFIG_CAM_GPIO_I2C*/ gpio_direction_output(CAM_SCL_GPIO, 1); gpio_direction_output(CAM_SDA_GPIO, 1); #endif gpio_direction_output(GC2015_STANDBY_GPIO, 0); //standby /*jhy add according to cam poweron timing end 2011.6.30*/ /* have to put sensor to reset to guarantee detection */ gpio_direction_output(GC2015_RESET_GPIO, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ gpio_direction_output(GC2015_RESET_GPIO, 1); printk(KERN_INFO "reset camera\n"); break; case V4L2_POWER_OFF: printk(KERN_INFO "GC2015_sensor_power_set(OFF)\n"); case V4L2_POWER_STANDBY: printk(KERN_INFO "GC2015_sensor_power_set(STANDBY)\n"); #ifndef KUNLUN_P0 /*kunlun P0 can't use GC2015_STANDBY_GPIO*/ gpio_direction_output(GC2015_STANDBY_GPIO, 0); //1 change by jhy for IOVDD has been close so standby no use 2011.6.30 udelay(20); gpio_direction_output(GC2015_RESET_GPIO, 0); udelay(20); //printk(KERN_DEBUG "GC2015_sensor_power_set(STANDBY)\n"); #endif /* Remove pm constraints */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); omap_pm_set_max_mpu_wakeup_lat(&qos_request, -1); /*jhy add according to cam poweron timing beg 2011.6.30*/ #if 1 /*definded CONFIG_CAM_GPIO_I2C*/ gpio_direction_output(CAM_SCL_GPIO, 0); gpio_direction_output(CAM_SDA_GPIO, 0); #endif /*jhy add according to cam poweron timing end 2011.6.30*/ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX2_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX3_DEV_GRP); //jhy add for Cam IOVDD ctrl 2011.6.30 /* Make sure not to disable the MCLK twice in a row */ if (previous_power == V4L2_POWER_ON) isp_disable_mclk(isp); break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
static int imx072_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); struct isp_csi2_lanes_cfg lanecfg; struct isp_csi2_phy_cfg phyconfig; static enum v4l2_power previous_power = V4L2_POWER_OFF; // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] static struct pm_qos_request_list *qos_request; // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] int err = 0; switch (power) { case V4L2_POWER_ON: /* Power Up Sequence */ printk(KERN_DEBUG "imx072_sensor_power_set(ON)\n"); /* * Through-put requirement: * Set max OCP freq for 3630 is 200 MHz through-put * is in KByte/s so 200000 KHz * 4 = 800000 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 800000); /* Hold a constraint to keep MPU in C1 */ // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] //omap_pm_set_max_mpu_wakeup_lat(vdev->cam->isp, 12); omap_pm_set_max_mpu_wakeup_lat(&qos_request, 12); /* 20110527 [email protected] camera l3 clock*/ // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] isp_csi2_reset(&isp->isp_csi2); lanecfg.clk.pol = IMX072_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = IMX072_CSI2_CLOCK_LANE; lanecfg.data[0].pol = IMX072_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = IMX072_CSI2_DATA0_LANE; lanecfg.data[1].pol = IMX072_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = IMX072_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0; lanecfg.data[2].pos = 0; lanecfg.data[3].pol = 0; lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg); isp_csi2_complexio_lanes_update(&isp->isp_csi2, true); isp_csi2_ctrl_config_ecc_enable(&isp->isp_csi2, true); phyconfig.ths_term = IMX072_CSI2_PHY_THS_TERM; phyconfig.ths_settle = IMX072_CSI2_PHY_THS_SETTLE; phyconfig.tclk_term = IMX072_CSI2_PHY_TCLK_TERM; phyconfig.tclk_miss = IMX072_CSI2_PHY_TCLK_MISS; phyconfig.tclk_settle = IMX072_CSI2_PHY_TCLK_SETTLE; isp_csi2_phy_config(&isp->isp_csi2, &phyconfig); isp_csi2_phy_update(&isp->isp_csi2, true); isp_configure_interface(vdev->cam->isp, &imx072_if_config); /* Request and configure gpio pins */ if (gpio_request(IMX072_RESET_GPIO, "imx072_rst") != 0) return -EIO; subpm_set_output(SWREG,1); subpm_output_enable(); subpm_set_output(LDO4,1); subpm_output_enable(); subpm_set_output(LDO3,1); subpm_output_enable(); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_1_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); udelay(100); /* have to put sensor to reset to guarantee detection */ gpio_direction_output(IMX072_RESET_GPIO, 1); // gpio_set_value(IMX072_RESET_GPIO, 1); udelay(100); // gpio_direction_output(IMX072_RESET_GPIO, 0); gpio_set_value(IMX072_RESET_GPIO, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ // gpio_direction_output(IMX072_RESET_GPIO, 1); gpio_set_value(IMX072_RESET_GPIO, 1); udelay(300); break; case V4L2_POWER_OFF: subpm_set_output(LDO5,0); subpm_output_enable(); gpio_set_value(DW9716_VCM_ENABLE, 0); isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); isp_csi2_reset(&isp->isp_csi2); isp_csi2_ctrl_config_ecc_enable(&isp->isp_csi2, true); isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); break; case V4L2_POWER_STANDBY: printk(KERN_DEBUG "imx072_sensor_power_set(%s)\n", (power == V4L2_POWER_OFF) ? "OFF" : "STANDBY"); /* Power Down Sequence */ isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); gpio_set_value(IMX072_RESET_GPIO, 0); udelay(5); subpm_set_output(LDO3,0); subpm_output_enable(); subpm_set_output(LDO4,0); subpm_output_enable(); subpm_set_output(SWREG,0); subpm_output_enable(); gpio_free(IMX072_RESET_GPIO); /* Remove pm constraints */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] //omap_pm_set_max_mpu_wakeup_lat(vdev->cam->isp, -1); omap_pm_set_max_mpu_wakeup_lat(&qos_request, -1); // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
static int mt9p012_sensor_power_set(struct device* dev, enum v4l2_power power) { static enum v4l2_power previous_power = V4L2_POWER_OFF; static struct regulator *regulator; switch (power) { case V4L2_POWER_OFF: /* Power Down Sequence */ gpio_free(GPIO_MT9P012_RESET); /* Turn off power */ if (regulator != NULL) { regulator_disable(regulator); regulator_put(regulator); regulator = NULL; } else { sholes_camera_lines_safe_mode(); pr_err("%s: Regulator for vcam is not "\ "initialized\n", __func__); return -EIO; } /* Release pm constraints */ omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, 0); sholes_camera_lines_safe_mode(); break; case V4L2_POWER_ON: if (previous_power == V4L2_POWER_OFF) { /* Power Up Sequence */ sholes_camera_lines_func_mode(); /* Set min throughput to: * 2592 x 1944 x 2bpp x 30fps x 3 L3 accesses */ omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, 885735); /* Configure pixel clock divider (here?) */ omap_writel(0x2, 0x48004f40); isp_configure_interface(&mt9p012_if_config); /* Request and configure gpio pins */ if (gpio_request(GPIO_MT9P012_RESET, "mt9p012 camera reset") != 0) return -EIO; /* set to output mode */ gpio_direction_output(GPIO_MT9P012_RESET, 0); /* nRESET is active LOW. set HIGH to release reset */ gpio_set_value(GPIO_MT9P012_RESET, 1); /* turn on digital power */ if (regulator != NULL) { pr_warning("%s: Already have "\ "regulator\n", __func__); } else { regulator = regulator_get(NULL, "vcam"); if (IS_ERR(regulator)) { pr_err("%s: Cannot get vcam "\ "regulator, err=%ld\n", __func__, PTR_ERR(regulator)); return PTR_ERR(regulator); } } if (regulator_enable(regulator) != 0) { pr_err("%s: Cannot enable vcam regulator\n", __func__); return -EIO; } } udelay(1000); if (previous_power == V4L2_POWER_OFF) { /* trigger reset */ gpio_direction_output(GPIO_MT9P012_RESET, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ gpio_set_value(GPIO_MT9P012_RESET, 1); /* give sensor sometime to get out of the reset. * Datasheet says 2400 xclks. At 6 MHz, 400 usec is * enough */ udelay(300); } break; case V4L2_POWER_STANDBY: /* Stand By Sequence */ break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return 0; }
/* * Stream management * * Every ISP pipeline has a single input and a single output. The input can be * either a sensor or a video node. The output is always a video node. * * As every pipeline has an output video node, the ISP video objects at the * pipeline output stores the pipeline state. It tracks the streaming state of * both the input and output, as well as the availability of buffers. * * In sensor-to-memory mode, frames are always available at the pipeline input. * Starting the sensor usually requires I2C transfers and must be done in * interruptible context. The pipeline is started and stopped synchronously * to the stream on/off commands. All modules in the pipeline will get their * subdev set stream handler called. The module at the end of the pipeline must * delay starting the hardware until buffers are available at its output. * * In memory-to-memory mode, starting/stopping the stream requires * synchronization between the input and output. ISP modules can't be stopped * in the middle of a frame, and at least some of the modules seem to become * busy as soon as they're started, even if they don't receive a frame start * event. For that reason frames need to be processed in single-shot mode. The * driver needs to wait until a frame is completely processed and written to * memory before restarting the pipeline for the next frame. Pipelined * processing might be possible but requires more testing. * * Stream start must be delayed until buffers are available at both the input * and output. The pipeline must be started in the videobuf queue callback with * the buffers queue spinlock held. The modules subdev set stream operation must * not sleep. */ static int isp_video_streamon(struct file *file, void *fh, enum v4l2_buf_type type) { struct isp_video_fh *vfh = to_isp_video_fh(fh); struct isp_video *video = video_drvdata(file); enum isp_pipeline_state state; struct isp_video *far_end; unsigned int streaming; unsigned long flags; int ret; if (type != video->type) return -EINVAL; mutex_lock(&video->stream_lock); mutex_lock(&vfh->queue.lock); streaming = vfh->queue.streaming; mutex_unlock(&vfh->queue.lock); if (video->pipe != NULL || streaming) { mutex_unlock(&video->stream_lock); return -EBUSY; } /* Lock the pipeline. No link touching an entity in the pipeline can * be activated or deactivated once the pipeline is locked. */ media_entity_graph_lock(&video->video.entity); /* Verify that the currently configured format matches the output of * the connected subdev. */ ret = isp_video_check_format(video, vfh); if (ret < 0) { printk(KERN_ERR "%s check format failed\n", __func__); goto error; } /* Find the ISP video node connected at the far end of the pipeline. */ far_end = isp_video_far_end(video); /* Update the pipeline state. */ if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { state = ISP_PIPELINE_STREAM_OUTPUT; video->pipe = &video->__pipe; video->pipe->input = far_end; video->pipe->output = video; } else { state = ISP_PIPELINE_STREAM_INPUT; video->pipe = &far_end->__pipe; video->pipe->input = video; video->pipe->output = far_end; } ret = isp_video_validate_pipeline(video->pipe); if (ret < 0) goto error; spin_lock_irqsave(&video->pipe->lock, flags); video->pipe->state |= state; spin_unlock_irqrestore(&video->pipe->lock, flags); /* * Formula from: resource34xx.c set_opp() * If MPU freq is above 500MHz, make sure the interconnect * is at 100Mhz or above. * throughput in KiB/s for 100 Mhz = 100 * 1000 * 4. * * We want to be fast enough then set OCP clock to be max as * possible, in that case 185Mhz then: * throughput in KiB/s for 185Mhz = 185 * 1000 * 4 = 740000 KiB/s */ omap_pm_set_min_bus_tput(video->isp->dev, OCP_INITIATOR_AGENT, 740000); video->queue = &vfh->queue; INIT_LIST_HEAD(&video->dmaqueue); atomic_set(&video->sequence, -1); ret = isp_video_queue_streamon(&vfh->queue); if (ret < 0) goto error; /* In sensor-to-memory mode, the stream can be started synchronously * to the stream on command. In memory-to-memory mode, it will be * started when buffers are queued on both the input and output. */ if (video->pipe->input == NULL) { ret = isp_pipeline_set_stream(video->isp, video, ISP_PIPELINE_STREAM_CONTINUOUS); if (ret < 0) goto error; } error: if (ret < 0) { isp_video_queue_streamoff(&vfh->queue); omap_pm_set_min_bus_tput(video->isp->dev, OCP_INITIATOR_AGENT, 0); media_entity_graph_unlock(&video->video.entity); video->pipe = NULL; video->queue = NULL; } mutex_unlock(&video->stream_lock); return ret; }
static ssize_t vdd_opp_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t n) { unsigned long value; static unsigned long prev_mpu_freq = 0; if (sscanf(buf, "%lu", &value) != 1) return -EINVAL; if (attr == &tick_control_attr) { if (value == 1) tick_nohz_disable(1); else if (value == 0) tick_nohz_disable(0); } /* Check locks */ if (attr == &vdd1_lock_attr) { if (vdd1_locked) { /* vdd1 currently locked */ if (value == 0) { omap_pm_cpu_set_freq(prev_mpu_freq * 1000); vdd1_locked = 0; return n; } else { printk(KERN_ERR "%s: vdd1 already locked to %d\n", __func__, vdd1_locked); return -EINVAL; } } else { /* vdd1 currently unlocked */ if (value != 0) { u8 i = 0; unsigned long freq = 0; struct cpufreq_frequency_table *freq_table = *omap_pm_cpu_get_freq_table(); if (freq_table == NULL) { printk(KERN_ERR "%s: Could not get freq_table\n", __func__); return -ENODEV; } for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { if (freq_table[i].index == value - 1) { freq = freq_table[i].frequency; break; } } if (freq_table[i].frequency == CPUFREQ_TABLE_END) { printk(KERN_ERR "%s: Invalid value [0..%d]\n", __func__, i-1); return -EINVAL; } prev_mpu_freq = omap_pm_cpu_get_freq(); omap_pm_cpu_set_freq(freq * 1000); vdd1_locked = value; } else { printk(KERN_ERR "%s: vdd1 already unlocked\n", __func__); return -EINVAL; } } } else if (attr == &vdd2_lock_attr) { if (vdd2_locked) { /* vdd2 currently locked */ if (value == 0) { int tmp_lock = vdd2_locked; vdd2_locked = 0; if (omap_pm_set_min_bus_tput(&sysfs_cpufreq_dev, OCP_INITIATOR_AGENT, -1)) { printk(KERN_ERR "%s: Failed to remove vdd2_lock\n", __func__); vdd2_locked = tmp_lock; /* restore previous lock */ } else { return n; } } else { printk(KERN_ERR "%s: vdd2 already locked to %d\n", __func__, vdd2_locked); return -EINVAL; } } else { /* vdd2 currently unlocked */ if (value != 0) { unsigned long freq = 0; if (cpu_is_omap3630()) { if(value == 1) { freq = 100*1000*4; } else if (value == 2) { freq = 200*1000*4; } else { printk(KERN_ERR "%s: Invalid value [1,2]\n", __func__); return -EINVAL; } } else if (cpu_is_omap44xx()) { if (omap_rev() <= OMAP4430_REV_ES2_0) { if(value == 1) { freq = 100*1000*4; } else if (value == 2) { freq = 200*1000*4; } else { printk(KERN_ERR "%s: Invalid value [1,2]\n", __func__); return -EINVAL; } } else { if(value == 1) { freq = 98304*4; } else if (value == 2) { freq = 100*1000*4; } else if (value == 3) { freq = 200*1000*4; } else { printk(KERN_ERR "%s: Invalid value [1,2,3]\n", __func__); return -EINVAL; } } } else { printk(KERN_ERR "%s: Unsupported HW [OMAP3630, OMAP44XX]\n", __func__); return -ENODEV; } if (omap_pm_set_min_bus_tput(&sysfs_cpufreq_dev, OCP_INITIATOR_AGENT, freq)) { printk(KERN_ERR "%s: Failed to add vdd2_lock\n", __func__); } else { vdd2_locked = value; } return n; } else { printk(KERN_ERR "%s: vdd2 already unlocked\n", __func__); return -EINVAL; } } } else if (attr == &dsp_freq_attr) { u8 i, opp_id = 0; struct omap_opp *opp_table = omap_pm_dsp_get_opp_table(); if (opp_table == NULL) { printk(KERN_ERR "%s: Could not get dsp opp_table\n", __func__); return -ENODEV; } for (i = 1; opp_table[i].rate; i++) { if (opp_table[i].rate >= value) { opp_id = i; break; } } if (opp_id == 0) { printk(KERN_ERR "%s: Invalid value\n", __func__); return -EINVAL; } omap_pm_dsp_set_min_opp(opp_id); } else if (attr == &vdd1_opp_attr) { printk(KERN_ERR "%s: changing vdd1_opp is not supported\n", __func__); return -EINVAL; } else if (attr == &vdd2_opp_attr) { printk(KERN_ERR "%s: changing vdd2_opp is not supported\n", __func__); return -EINVAL; } else { return -EINVAL; } return n; }
static int rpres_set_l3_bw(struct platform_device *pdev, long val) { return omap_pm_set_min_bus_tput(&pdev->dev, OCP_INITIATOR_AGENT, val); }
static int S5K5CA_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); static enum v4l2_power previous_power = V4L2_POWER_OFF; static struct pm_qos_request_list *qos_request; int err = 0; printk(KERN_INFO "previous_power = %d,S5K5CA_sensor_power_set(%d)\n",previous_power,power); switch (power) { case V4L2_POWER_ON: /* Through-put requirement: * 3280 x 2464 x 2Bpp x 7.5fps x 3 memory ops = 355163 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 664000); // 276480); /* Hold a constraint to keep MPU in C1 */ omap_pm_set_max_mpu_wakeup_lat(&qos_request, 12); isp_configure_interface(vdev->cam->isp,&S5K5CA_if_config); /* turn on analog power */ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX2_1_5_V, TWL4030_VAUX2_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX2_DEV_GRP); udelay(600); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_2_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); udelay(100); printk(KERN_INFO "VAUX4 = 2.8V\n"); gpio_direction_output(S5K5CA_RESET_GPIO, 0); printk(KERN_INFO "reset camera\n"); udelay(20); gpio_direction_output(S5K5CA_STANDBY_GPIO, 1); udelay(20); gpio_direction_output(S5K5CA_RESET_GPIO, 1); //udelay(20); break; case V4L2_POWER_OFF: printk(KERN_INFO "S5K5CA_sensor_power_set(OFF)\n"); break; case V4L2_POWER_STANDBY: printk(KERN_INFO "S5K5CA_sensor_power_set(STANDBY)\n"); /* Remove pm constraints */ gpio_direction_output(S5K5CA_STANDBY_GPIO, 0); mdelay(50); omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); omap_pm_set_max_mpu_wakeup_lat(&qos_request, -1); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX2_DEV_GRP); /* Make sure not to disable the MCLK twice in a row */ if (previous_power == V4L2_POWER_ON) isp_disable_mclk(isp); break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
static int ov2659_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); static enum v4l2_power previous_power = V4L2_POWER_OFF; static struct pm_qos_request_list *qos_request; int err = 0; printk(KERN_INFO "previous_power = %d,ov2659_sensor_power_set(%d)\n",previous_power,power); switch (power) { case V4L2_POWER_ON: /* Through-put requirement: * 3280 x 2464 x 2Bpp x 7.5fps x 3 memory ops = 355163 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 664000); /* Hold a constraint to keep MPU in C1 */ omap_pm_set_max_mpu_wakeup_lat(&qos_request, 12); isp_configure_interface(vdev->cam->isp,&ov2659_if_config); udelay(20); #if OV2659_USE_STANDBY //add standby mode for cam open speed up jhy 2011.09.09 if (previous_power == V4L2_POWER_OFF) { gpio_direction_output(OV2659_STANDBY_GPIO, 0); //standby gpio_direction_output(OV2659_RESET_GPIO, 1); /* turn on analog & IO power jhy add VAUX3 Ctrl 2011.6.30*/ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX3_1_8_V, TWL4030_VAUX3_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX3_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, TWL4030_VAUX_REMAP_VALUE, TWL4030_VAUX3_REMAP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX2_1_5_V, TWL4030_VAUX2_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX2_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, TWL4030_VAUX_REMAP_VALUE, TWL4030_VAUX2_REMAP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_2_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, TWL4030_VAUX_REMAP_VALUE, TWL4030_VAUX4_REMAP); udelay(100); //printk(KERN_INFO "VAUX4 = 2.8V\n"); /* have to put sensor to reset to guarantee detection */ gpio_direction_output(OV2659_RESET_GPIO, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ gpio_direction_output(OV2659_RESET_GPIO, 1); } else { gpio_direction_output(OV2659_STANDBY_GPIO, 0); printk(KERN_INFO "camera(OV2659) exit standby\n"); } #else gpio_direction_output(OV2659_STANDBY_GPIO, 0); //standby gpio_direction_output(OV2659_RESET_GPIO, 1); /* turn on analog & IO power jhy add VAUX3 Ctrl 2011.6.30*/ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX3_1_8_V, TWL4030_VAUX3_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX3_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX2_1_5_V, TWL4030_VAUX2_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX2_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_2_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); udelay(100); //printk(KERN_INFO "VAUX4 = 2.8V\n"); /* have to put sensor to reset to guarantee detection */ gpio_direction_output(OV2659_RESET_GPIO, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ gpio_direction_output(OV2659_RESET_GPIO, 1); #endif //printk(KERN_INFO "reset camera\n"); break; case V4L2_POWER_OFF: printk(KERN_INFO "OV2659_sensor_power_set(OFF)\n"); case V4L2_POWER_STANDBY: /* Remove pm constraints */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); omap_pm_set_max_mpu_wakeup_lat(&qos_request, -1); #if OV2659_USE_STANDBY // standby mode for cam jhy 2011.09.09 gpio_direction_output(OV2659_STANDBY_GPIO, 1); #else gpio_direction_output(OV2659_STANDBY_GPIO, 0); gpio_direction_output(OV2659_RESET_GPIO, 0); #if 1 /*definded CONFIG_CAM_GPIO_I2C */ gpio_direction_output(CAM_SCL_GPIO, 0); gpio_direction_output(CAM_SDA_GPIO, 0); #endif twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX2_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX3_DEV_GRP); //jhy add for Cam IOVDD ctrl 2011.6.30 #endif /* Make sure not to disable the MCLK twice in a row */ if (previous_power == V4L2_POWER_ON) isp_disable_mclk(isp); break; } #if !OV2659_USE_STANDBY /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; #endif return err; }
/*! ****************************************************************************** @Function EnableSGXClocks @Description Enable SGX clocks @Return PVRSRV_ERROR ******************************************************************************/ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData) { #if !defined(NO_HARDWARE) SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; /* SGX clocks already enabled? */ if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0) { return PVRSRV_OK; } PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks")); #if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) #if defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK) { struct gpu_platform_data *pdata; IMG_UINT32 max_freq_index; int res; pdata = (struct gpu_platform_data *)gpsPVRLDMDev->dev.platform_data; max_freq_index = psSysSpecData->ui32SGXFreqListSize - 2; /* * Request maximum frequency from DVFS layer if not already set. DVFS may * report busy if early in initialization, but all other errors are * considered serious. Upon any error we proceed assuming our safe frequency * value to be in use as indicated by the "unknown" index. */ if (psSysSpecData->ui32SGXFreqListIndex != max_freq_index) { PVR_ASSERT(pdata->device_scale != IMG_NULL); res = pdata->device_scale(&gpsPVRLDMDev->dev, &gpsPVRLDMDev->dev, psSysSpecData->pui32SGXFreqList[max_freq_index]); if (res == 0) { psSysSpecData->ui32SGXFreqListIndex = max_freq_index; } else if (res == -EBUSY) { PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Unable to scale SGX frequency (EBUSY)")); psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1; } else if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Unable to scale SGX frequency (%d)", res)); psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1; } } } #endif /* defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK) */ { /* * pm_runtime_get_sync returns 1 after the module has * been reloaded. */ int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res)); return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; } } #endif /* defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) */ SysEnableSGXInterrupts(psSysData); #if !defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK) if (cpu_is_omap3430()) { /* pin the memory bus bw to the highest value */ omap_pm_set_min_bus_tput(&gpsPVRLDMDev->dev, OCP_INITIATOR_AGENT, 400000); } else if (cpu_is_omap3630()) { /* pin the memory bus bw to the highest value */ omap_pm_set_min_bus_tput(&gpsPVRLDMDev->dev, OCP_INITIATOR_AGENT, 800000); } else { PVR_DPF((PVR_DBG_ERROR, "ForceMaxSGXClocks: \ Invalid OMAP Chip ID")); return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; } #endif /* Indicate that the SGX clocks are enabled */ atomic_set(&psSysSpecData->sSGXClocksEnabled, 1); #else /* !defined(NO_HARDWARE) */ PVR_UNREFERENCED_PARAMETER(psSysData); #endif /* !defined(NO_HARDWARE) */ return PVRSRV_OK; }
static int yacd5b1s_sensor_power_set(struct v4l2_int_device *dev, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = dev->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); static enum v4l2_power previous_power = V4L2_POWER_OFF; static struct pm_qos_request_list *qos_request_sec; /* 20110527 [email protected] camera l3 clock*/ int err = 0; switch (power) { case V4L2_POWER_ON: /* Power Up Sequence */ printk(KERN_DEBUG "yacd5b1s_sensor_power_set(ON)\n"); // [email protected] [TBD]Temporarily block the following code because PM APIs have been changed [START] #if 1 omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 800000); /* Hold a constraint to keep MPU in C1 */ omap_pm_set_max_mpu_wakeup_lat(&qos_request_sec, 12); /* 20110527 [email protected] camera l3 clock*/ #endif // [email protected] [TBD]Temporarily block the following code because PM APIs have been changed [END] isp_configure_interface(vdev->cam->isp,&yacd5b1s_if_config); if (gpio_request(YACD5B1S_RESET_GPIO, "yacd5b1s_rst") != 0) printk("\n\n\n>>>>>>>>>>>>YACD5B1S_RESET_GPIO_gpio_request_error\n\n\n");//return -EIO; if (gpio_request(YACD5B1S_STANDBY_GPIO, "yacd5b1s_PWD") != 0) printk("\n\n\n>>>>>>>>>>>>YACD5B1S_STANDBY_GPIO_gpio_request_error\n\n\n");//return -EIO;return -EIO; #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, SET_VMMC1_V2_8,VMMC1_DEDICATED ); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VMMC1_DEV_GRP_P1,VMMC1_DEV_GRP ); #endif udelay(20); #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX3_1_8_V, TWL4030_VAUX3_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX3_DEV_GRP); #endif twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_1_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); //wait typical 500ms for xclk to settle //mdelay(500); gpio_direction_output(YACD5B1S_STANDBY_GPIO, true); udelay(100); gpio_set_value(YACD5B1S_STANDBY_GPIO, 0); udelay(1500); gpio_set_value(YACD5B1S_STANDBY_GPIO, 1); mdelay(100); udelay(50); gpio_direction_output(YACD5B1S_RESET_GPIO, true); udelay(100); gpio_set_value(YACD5B1S_RESET_GPIO, 0); /* set to output mode */ udelay(1500); gpio_set_value(YACD5B1S_RESET_GPIO, 1); udelay(300); break; case V4L2_POWER_OFF: printk(KERN_DEBUG "yacd5b1s_sensor_power_set(OFF)\n"); /* Power Down Sequence */ gpio_set_value(YACD5B1S_RESET_GPIO, 0); udelay(50); gpio_set_value(YACD5B1S_STANDBY_GPIO, 0); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE,VMMC1_DEV_GRP ); #endif #if 1 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX3_DEV_GRP); #endif gpio_free(YACD5B1S_STANDBY_GPIO); gpio_free(YACD5B1S_RESET_GPIO); // [email protected] [TBD]Temporarily block the following code because PM APIs have been changed [START] #if 1 omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); omap_pm_set_max_mpu_wakeup_lat(&qos_request_sec, -1); #endif // [email protected] [TBD]Temporarily block the following code because PM APIs have been changed [END] break; case V4L2_POWER_STANDBY: printk(KERN_DEBUG "yacd5b1s_sensor_power_set(STANDBY)\n"); gpio_set_value(YACD5B1S_RESET_GPIO, 0); udelay(50); gpio_set_value(YACD5B1S_STANDBY_GPIO, 0); udelay(50); gpio_free(YACD5B1S_STANDBY_GPIO); gpio_free(YACD5B1S_RESET_GPIO); break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
/*! ****************************************************************************** @Function DisableSGXClocks @Description Disable SGX clocks. @Return none ******************************************************************************/ IMG_VOID DisableSGXClocks(SYS_DATA *psSysData) { #if !defined(NO_HARDWARE) SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; /* SGX clocks already disabled? */ if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0) { return; } PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks")); #if !defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK) omap_pm_set_min_bus_tput(&gpsPVRLDMDev->dev, OCP_INITIATOR_AGENT, 0); #endif SysDisableSGXInterrupts(psSysData); #if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) { int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res)); } } #if defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK) { struct gpu_platform_data *pdata; int res; pdata = (struct gpu_platform_data *)gpsPVRLDMDev->dev.platform_data; /* * Request minimum frequency (list index 0) from DVFS layer if not already * set. DVFS may report busy if early in initialization, but all other errors * are considered serious. Upon any error we proceed assuming our safe frequency * value to be in use as indicated by the "unknown" index. */ if (psSysSpecData->ui32SGXFreqListIndex != 0) { PVR_ASSERT(pdata->device_scale != IMG_NULL); res = pdata->device_scale(&gpsPVRLDMDev->dev, &gpsPVRLDMDev->dev, psSysSpecData->pui32SGXFreqList[0]); if (res == 0) { psSysSpecData->ui32SGXFreqListIndex = 0; } else if (res == -EBUSY) { PVR_DPF((PVR_DBG_WARNING, "DisableSGXClocks: Unable to scale SGX frequency (EBUSY)")); psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1; } else if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: Unable to scale SGX frequency (%d)", res)); psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1; } } } #endif /* defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK) */ #endif /* defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) */ /* Indicate that the SGX clocks are disabled */ atomic_set(&psSysSpecData->sSGXClocksEnabled, 0); #else /* !defined(NO_HARDWARE) */ PVR_UNREFERENCED_PARAMETER(psSysData); #endif /* !defined(NO_HARDWARE) */ }
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData) { #if !defined(NO_HARDWARE) SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; long lNewRate; long lRate; IMG_INT res; if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0) { return PVRSRV_OK; } PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks")); #if defined(DEBUG) { IMG_UINT32 rate = clk_get_rate(psSysSpecData->psMPU_CK); PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: CPU Clock is %dMhz", HZ_TO_MHZ(rate))); } #endif res = clk_enable(psSysSpecData->psSGX_FCK); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res)); return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; } res = clk_enable(psSysSpecData->psSGX_ICK); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX interface clock (%d)", res)); clk_disable(psSysSpecData->psSGX_FCK); return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; } lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ); if (lNewRate <= 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate")); return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE; } lRate = clk_get_rate(psSysSpecData->psSGX_FCK); if (lRate != lNewRate) { res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate); if (res < 0) { PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res)); } } IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK); //Get the functional clock printk(KERN_DEBUG "EnableSGXClocks: SGX Functional Clock is %dMhz\n", HZ_TO_MHZ(rate)); #if defined(SYS_OMAP3430_PIN_MEMORY_BUS_CLOCK) omap_pm_set_min_bus_tput(&gpsPVRLDMDev->dev, OCP_INITIATOR_AGENT, OMAP_MEMORY_BUS_CLOCK_MAX); #endif atomic_set(&psSysSpecData->sSGXClocksEnabled, 1); #else /* !defined(NO_HARDWARE) */ PVR_UNREFERENCED_PARAMETER(psSysData); #endif /* !defined(NO_HARDWARE) */ return PVRSRV_OK; }
static int omap3_evm_enable_tv(struct omap_dss_device *dssdev) { omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 400000); return 0; }
static int imx072_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power power) { struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); struct isp_csi2_lanes_cfg lanecfg; struct isp_csi2_phy_cfg phyconfig; static enum v4l2_power previous_power = V4L2_POWER_OFF; // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] static struct pm_qos_request_list *qos_request; // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] int err = 0; switch (power) { case V4L2_POWER_ON: /* Power Up Sequence */ printk(KERN_DEBUG "imx072_sensor_power_set(ON)\n"); /* * Through-put requirement: * Set max OCP freq for 3630 is 200 MHz through-put * is in KByte/s so 200000 KHz * 4 = 800000 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 800000); /* Hold a constraint to keep MPU in C1 */ // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] //omap_pm_set_max_mpu_wakeup_lat(vdev->cam->isp, 12); omap_pm_set_max_mpu_wakeup_lat(&qos_request, 12); // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] isp_csi2_reset(&isp->isp_csi2); lanecfg.clk.pol = IMX072_CSI2_CLOCK_POLARITY; lanecfg.clk.pos = IMX072_CSI2_CLOCK_LANE; lanecfg.data[0].pol = IMX072_CSI2_DATA0_POLARITY; lanecfg.data[0].pos = IMX072_CSI2_DATA0_LANE; lanecfg.data[1].pol = IMX072_CSI2_DATA1_POLARITY; lanecfg.data[1].pos = IMX072_CSI2_DATA1_LANE; lanecfg.data[2].pol = 0; lanecfg.data[2].pos = 0; lanecfg.data[3].pol = 0; lanecfg.data[3].pos = 0; isp_csi2_complexio_lanes_config(&isp->isp_csi2, &lanecfg); isp_csi2_complexio_lanes_update(&isp->isp_csi2, true); isp_csi2_ctrl_config_ecc_enable(&isp->isp_csi2, true); phyconfig.ths_term = IMX072_CSI2_PHY_THS_TERM; phyconfig.ths_settle = IMX072_CSI2_PHY_THS_SETTLE; phyconfig.tclk_term = IMX072_CSI2_PHY_TCLK_TERM; phyconfig.tclk_miss = IMX072_CSI2_PHY_TCLK_MISS; phyconfig.tclk_settle = IMX072_CSI2_PHY_TCLK_SETTLE; isp_csi2_phy_config(&isp->isp_csi2, &phyconfig); isp_csi2_phy_update(&isp->isp_csi2, true); isp_configure_interface(vdev->cam->isp, &imx072_if_config); /* Request and configure gpio pins */ if (gpio_request(IMX072_RESET_GPIO, "imx072_rst") != 0) return -EIO; subpm_set_output(SWREG,1); subpm_output_enable(); subpm_set_output(LDO4,1); subpm_output_enable(); subpm_set_output(LDO3,1); subpm_output_enable(); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_1_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); udelay(100); /* have to put sensor to reset to guarantee detection */ gpio_direction_output(IMX072_RESET_GPIO, 1); // gpio_set_value(IMX072_RESET_GPIO, 1); udelay(100); // gpio_direction_output(IMX072_RESET_GPIO, 0); gpio_set_value(IMX072_RESET_GPIO, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ // gpio_direction_output(IMX072_RESET_GPIO, 1); gpio_set_value(IMX072_RESET_GPIO, 1); udelay(300); break; case V4L2_POWER_OFF: //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM printk(KERN_DEBUG "imx072_sensor_power_set(OFF)\n"); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM subpm_set_output(LDO5,0); subpm_output_enable(); gpio_set_value(DW9716_VCM_ENABLE, 0); //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM /* This is not required cuz it is disabled in isp_csi_memvs.c*/ /* isp_disable_mclk(isp); */ //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); isp_csi2_reset(&isp->isp_csi2); isp_csi2_ctrl_config_ecc_enable(&isp->isp_csi2, true); isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM /* check before disabling to avoid warning - because the STANDBY disables the clock */ /*OMAPS00234165 */ if (previous_power == V4L2_POWER_ON) isp_disable_mclk(isp); //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM break; case V4L2_POWER_STANDBY: //--[[ LGE_UBIQUIX_MODIFIED_START : [email protected] [2011.07.26] - CAM #ifdef CONFIG_OMAP2_DSS_HDMI { extern int hdmi_power_initialize; int hdmi_wait_cnt = 0; for(hdmi_wait_cnt = 0; hdmi_wait_cnt<20; hdmi_wait_cnt++) { if (hdmi_power_initialize== 0) { printk("==========================================================\n"); printk("waiting DONE for HDMI : %d looping \n", hdmi_wait_cnt); printk("==========================================================\n"); break; } printk("==========================================================\n"); printk("HDMI is not done yet...waiting for HDMI DONE : %d looping \n", hdmi_wait_cnt); printk("==========================================================\n"); msleep(100); } } #endif //--]] LGE_UBIQUIX_MODIFIED_END : [email protected] [2011.07.26] - CAM printk(KERN_DEBUG "imx072_sensor_power_set(%s)\n", (power == V4L2_POWER_OFF) ? "OFF" : "STANDBY"); /* Power Down Sequence */ isp_csi2_complexio_power(&isp->isp_csi2, ISP_CSI2_POWER_OFF); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); gpio_set_value(IMX072_RESET_GPIO, 0); udelay(5); subpm_set_output(LDO3,0); subpm_output_enable(); subpm_set_output(LDO4,0); subpm_output_enable(); subpm_set_output(SWREG,0); subpm_output_enable(); gpio_free(IMX072_RESET_GPIO); /* Remove pm constraints */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, -1); // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [START] //omap_pm_set_max_mpu_wakeup_lat(vdev->cam->isp, -1); omap_pm_set_max_mpu_wakeup_lat(&qos_request, -1); // 20110426 [email protected] Update omap_pm_set_max_mpu_wakeup_lat() for 2.6.35 kernel [END] /* Make sure not to disable the MCLK twice in a row */ if (previous_power == V4L2_POWER_ON) isp_disable_mclk(isp); break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }
static int omap_rproc_set_l3_bw(struct rproc *rproc, long val) { return omap_pm_set_min_bus_tput(rproc->dev, OCP_INITIATOR_AGENT, val); }
static int hi253_power_set(struct v4l2_int_device *s, enum v4l2_power power,u8 type) { struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; struct isp_device *isp = dev_get_drvdata(vdev->cam->isp); static enum v4l2_power previous_power = V4L2_POWER_OFF; static struct pm_qos_request_list *qos_request; int err = 0; printk(KERN_ERR "previous_power = %d,Hi253_sensor_power_set(%d)\n",previous_power,power); switch (power) { case V4L2_POWER_ON: /* * Through-put requirement: * Set max OCP freq for 3630 is 200 MHz through-put * is in KByte/s so 200000 KHz * 4 = 800000 KByte/s */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 800000); /* Hold a constraint to keep MPU in C1 */ omap_pm_set_max_mpu_wakeup_lat(&qos_request, 12); isp_configure_interface(vdev->cam->isp,&Hi253_if_config); gpio_direction_output(BF3703_STANDBY_GPIO,1); gpio_direction_output(HI253_STANDBY_GPIO, 0); udelay(10); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_2_8_V, TWL4030_VAUX4_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_P1, TWL4030_VAUX4_DEV_GRP); udelay(100); printk(KERN_ERR "VAUX4 = 2.8V\n"); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VMMC2_1_5_V, TWL4030_VMMC2_DEDICATED); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VMMC2_DEV_GRP_P1, TWL4030_VMMC2_DEV_GRP); udelay(100); printk(KERN_ERR "VMMC2 = 1.5V\n"); gpio_direction_output(HI253_RESET_GPIO, 1); mdelay(1); /* have to put sensor to reset to guarantee detection */ gpio_direction_output(HI253_RESET_GPIO, 0); udelay(1500); /* nRESET is active LOW. set HIGH to release reset */ gpio_direction_output(HI253_RESET_GPIO, 1); printk(KERN_ERR "reset camera(HI253)\n"); break; case V4L2_POWER_OFF: case V4L2_POWER_STANDBY: printk(KERN_ERR "_sensor_power_set(OFF )\n"); gpio_direction_output(HI253_STANDBY_GPIO, 1); printk(KERN_DEBUG "hi253_sensor_power_set(STANDBY)\n"); /* Remove pm constraints */ omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); omap_pm_set_max_mpu_wakeup_lat(&qos_request, -1); /* twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VAUX4_DEV_GRP); twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, VAUX_DEV_GRP_NONE, TWL4030_VMMC2_DEV_GRP); */ /* Make sure not to disable the MCLK twice in a row */ if (previous_power == V4L2_POWER_ON){ isp_disable_mclk(isp); } break; // printk(KERN_ERR "_sensor_power_set(STANDBY)\n"); break; } /* Save powerstate to know what was before calling POWER_ON. */ previous_power = power; return err; }