int __init omap3_twl_init(void)
{
struct voltagedomain *voltdm;
if (!cpu_is_omap34xx() || cpu_is_am33xx())
return -ENODEV;
if (cpu_is_omap3630()) {
omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
/*
* The smartreflex bit on twl4030 specifies if the setting of voltage
* is done over the I2C_SR path. Since this setting is independent of
* the actual usage of smartreflex AVS module, we enable TWL SR bit
* by default irrespective of whether smartreflex AVS module is enabled
* on the OMAP side or not. This is because without this bit enabled,
* the voltage scaling through vp forceupdate/bypass mechanism of
* voltage scaling will not function on TWL over I2C_SR.
*/
if (!twl_sr_enable_autoinit)
omap3_twl_set_sr_bit(true);
voltdm = voltdm_lookup("mpu_iva");
omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
voltdm = voltdm_lookup("core");
omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
return 0;
}
static void __init omap_evt_init(void)
{
printk(">>> omap_evt_init\n");
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
evt_peripherals_init();
pr_info("CPU variant: %s\n", cpu_is_omap3622()? "OMAP3622": "OMAP3621");
#ifdef CONFIG_PM
#ifdef CONFIG_TWL4030_CORE
omap_voltage_register_pmic(&omap_pmic_core, "core");
omap_voltage_register_pmic(&omap_pmic_mpu, "mpu");
#endif
omap_voltage_init_vc(&vc_config);
#endif
//omap3xxx_hwmod_init();
//omap_mux_init_gpio(64, OMAP_PIN_OUTPUT);
usb_ehci_init(&ehci_pdata);
conn_add_plat_device();
printk("<<< omap_evt_init\n");
}
int __init omap4_twl_init(void)
{
struct voltagedomain *voltdm;
if (!cpu_is_omap44xx())
return -ENODEV;
voltdm = voltdm_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
voltdm = voltdm_lookup("iva");
omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
voltdm = voltdm_lookup("core");
omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
return 0;
}
int __init omap3_twl_init(void)
{
struct voltagedomain *voltdm;
if (!cpu_is_omap34xx())
return -ENODEV;
voltdm = omap_voltage_domain_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
return 0;
}
int __init omap3_twl_init(void)
{
struct voltagedomain *voltdm;
if (!cpu_is_omap34xx())
return -ENODEV;
/*
* In case of AM3517/AM3505 we should not be going down
* further, since SR is not applicable there.
*/
if (cpu_is_omap3505() || cpu_is_omap3517())
return -ENODEV;
if (cpu_is_omap3630()) {
omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
/*
* The smartreflex bit on twl4030 needs to be enabled by
* default irrespective of whether smartreflex module is
* enabled on the OMAP side or not. This is because without
* this bit enabled the voltage scaling through
* vp forceupdate does not function properly on OMAP3.
*/
if (twl_sr_enable)
omap3_twl_set_sr_bit(1);
voltdm = omap_voltage_domain_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
voltdm = omap_voltage_domain_lookup("core");
omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
return 0;
}
int __init omap3_twl_init(void)
{
struct voltagedomain *voltdm;
if (!cpu_is_omap34xx())
return -ENODEV;
if (cpu_is_omap3630()) {
omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
voltdm = omap_voltage_domain_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
voltdm = omap_voltage_domain_lookup("core");
omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
return 0;
}
/**
* omap_pmic_register_data() - Register the PMIC information to OMAP mapping
* @omap_pmic_maps: array ending with a empty element representing the maps
* @desc: description for this PMIC.
*/
int __init omap_pmic_register_data(struct omap_pmic_map *omap_pmic_maps,
struct omap_pmic_description *desc)
{
struct voltagedomain *voltdm;
struct omap_pmic_map *map;
int r;
if (!omap_pmic_maps)
return 0;
map = omap_pmic_maps;
while (map->name) {
if (!omap_chip_is(map->omap_chip))
goto next;
/* The base PMIC is the one controlling core voltdm */
if (desc && !strcmp(map->name, "core"))
omap_pm_set_pmic_lp_time(desc->pmic_lp_tstart,
desc->pmic_lp_tshut);
voltdm = voltdm_lookup(map->name);
if (IS_ERR_OR_NULL(voltdm)) {
pr_err("%s: unable to find map %s\n", __func__,
map->name);
goto next;
}
if (IS_ERR_OR_NULL(map->pmic_data)) {
pr_warning("%s: domain[%s] has no pmic data\n",
__func__, map->name);
goto next;
}
r = omap_voltage_register_pmic(voltdm, map->pmic_data);
if (r) {
pr_warning("%s: domain[%s] register returned %d\n",
__func__, map->name, r);
goto next;
}
if (map->special_action) {
r = map->special_action(voltdm);
WARN(r, "%s: domain[%s] action returned %d\n", __func__,
map->name, r);
}
next:
map++;
}
return 0;
}
void __init acclaim_peripherals_init(void)
{
int status;
int package = OMAP_PACKAGE_CBS;
ulong sdram_size = get_sdram_size();
ramconsole_init();
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, package);
acclaim_board_init();
if (sdram_vendor() == SAMSUNG_SDRAM) {
if (sdram_size == SZ_512M) {
omap_emif_setup_device_details(&emif_devices_512_samsung, &emif_devices_512_samsung);
} else if (sdram_size == SZ_1G) {
omap_emif_setup_device_details(&emif_devices_samsung, &emif_devices_samsung);
} else {
pr_err("sdram memory size does not exist, default to using 1024MB \n");
omap_emif_setup_device_details(&emif_devices_samsung, &emif_devices_samsung);
}
printk(KERN_INFO"Samsung DDR Memory \n");
} else if (sdram_vendor() == ELPIDA_SDRAM) {
if (sdram_size == SZ_512M) {
omap_emif_setup_device_details(&emif_devices_512_elpida, &emif_devices_512_elpida);
} else if (sdram_size == SZ_1G) {
omap_emif_setup_device_details(&emif_devices_elpida, &emif_devices_elpida);
} else {
pr_err("sdram memory size does not exist, default to using 1024MB \n");
omap_emif_setup_device_details(&emif_devices_elpida, &emif_devices_elpida);
}
printk(KERN_INFO"Elpida DDR Memory \n");
} else if (sdram_vendor() == HYNIX_SDRAM) {
/* Re-use ELPIDA timings as they are absolutely the same */
if (sdram_size == SZ_512M) {
omap_emif_setup_device_details(&emif_devices_512_elpida, &emif_devices_512_elpida);
} else if (sdram_size == SZ_1G) {
omap_emif_setup_device_details(&emif_devices_elpida, &emif_devices_elpida);
} else {
pr_err("sdram memory size does not exist, default to using 1024MB \n");
omap_emif_setup_device_details(&emif_devices_elpida, &emif_devices_elpida);
}
printk(KERN_INFO"Hynix DDR Memory \n");
} else
pr_err("Memory type does not exist\n");
omap_init_emif_timings();
enable_rtc_gpio();
omap4_i2c_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
acclaim_init_charger();
wake_lock_init(&uart_lock, WAKE_LOCK_SUSPEND, "uart_wake_lock");
omap_serial_init(omap_serial_platform_data);
omap4_twl6030_hsmmc_init(mmc);
#ifdef CONFIG_TIWLAN_SDIO
config_wlan_mux();
#else
//omap4_4430sdp_wifi_init();
#endif
kxtf9_dev_init();
#ifdef CONFIG_BATTERY_MAX17042
max17042_dev_init();
#endif
usb_uhhtll_init(&usbhs_pdata);
usb_musb_init(&musb_board_data);
status = omap4_keypad_initialization(&sdp4430_keypad_data);
if (status)
pr_err("Keypad initialization failed: %d\n", status);
spi_register_board_info(sdp4430_spi_board_info,
ARRAY_SIZE(sdp4430_spi_board_info));
acclaim_panel_init();
enable_board_wakeup_source();
omap_voltage_register_pmic(&omap_pmic_core, "core");
omap_voltage_register_pmic(&omap_pmic_mpu, "mpu");
omap_voltage_register_pmic(&omap_pmic_iva, "iva");
omap_voltage_init_vc(&vc_config);
}
