int main(void)
{
// Configure pin 7 on EXT1 as output
ioport_configure_pin(EXT1_PIN_7,IOPORT_DIR_OUTPUT);
sysclk_init();
board_init();
// Start TC and configure pin to get PWM output to LED on IO1 Xplained Pro extension board
tc_init();
while (1) {
struct pll_config pcfg;
/*
* Initial state: Running from RC32M prescalers with 16x
* prescaling of CLKsys, 2x prescaling for CLKper2 and 2x
* prescaling for CLKper.
*/
wait_for_btn_press();
/*
* Prescale CLKsys by 128x, prescale all peripheral clocks by 1.
*/
sysclk_set_prescalers(SYSCLK_PSADIV_128, SYSCLK_PSBCDIV_1_1);
wait_for_btn_press();
/*
* Switch to RC2M with 4x prescaling of CLKsys, 4x prescaling
* for CLKper2 and 1x prescaling for CLKper.
*/
osc_enable(OSC_ID_RC2MHZ);
do {} while (!osc_is_ready(OSC_ID_RC2MHZ));
sysclk_set_source(SYSCLK_SRC_RC2MHZ);
sysclk_set_prescalers(SYSCLK_PSADIV_4, SYSCLK_PSBCDIV_4_1);
osc_disable(OSC_ID_RC32MHZ);
wait_for_btn_press();
/*
* Switch to PLL with RC2M as reference and 4x multiplier.
* Prescale CLKsys by 128x, and all peripheral clocks by 1x.
*/
pll_config_init(&pcfg, PLL_SRC_RC2MHZ, 1, 4);
pll_enable(&pcfg, 0);
do {} while (!pll_is_locked(0));
sysclk_set_prescalers(SYSCLK_PSADIV_128, SYSCLK_PSBCDIV_1_1);
sysclk_set_source(SYSCLK_SRC_PLL);
wait_for_btn_press();
/*
* Go back to the initial state and start over.
*/
osc_enable(OSC_ID_RC32MHZ);
do {} while(!osc_is_ready(OSC_ID_RC32MHZ));
sysclk_set_source(SYSCLK_SRC_RC32MHZ);
sysclk_set_prescalers(SYSCLK_PSADIV_16, SYSCLK_PSBCDIV_2_2);
pll_disable(0);
osc_disable(OSC_ID_RC2MHZ);
}
}
/**
* \brief Event Manager QTouch Init.
*/
void event_qtouch_init(void)
{
struct ast_config ast_conf;
// Enable Osc32
osc_enable(OSC_ID_OSC32);
while(!osc_is_ready(OSC_ID_OSC32));
// Initialize AST Controller
ast_enable(AST);
ast_conf.mode = AST_COUNTER_MODE;
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = AST_PSEL_32KHZ_1HZ;
ast_conf.counter = 0;
ast_set_config(AST, &ast_conf);
ast_clear_interrupt_flag(AST, AST_INTERRUPT_PER);
ast_write_periodic0_value(AST, 9);
ast_set_callback(AST, AST_INTERRUPT_PER, ast_per_callback,
AST_PER_IRQn, 0);
//CATB & Related clocks - for QTouch Sensors
sysclk_enable_peripheral_clock(CATB);
sysclk_enable_peripheral_clock(PDCA);
// Initialize QTouch Library.
touch_sensors_init();
}
/**
* Initialize the AST as event generator.
*/
static void init_ast(void)
{
struct ast_config ast_conf;
/* Enable osc32 oscillator */
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
/* Enable the AST */
ast_enable(AST);
/* Configure the AST with counter mode and set counter to 0 */
ast_conf.mode = AST_COUNTER_MODE;
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = AST_PSEL_32KHZ_1HZ;
ast_conf.counter = 0;
ast_set_config(AST, &ast_conf);
/* Enable period enent of AST */
ast_write_periodic0_value(AST, AST_PSEL_32KHZ_1HZ);
ast_enable_event(AST, AST_EVENT_PER);
}
/**
* \brief Run PICOUART driver unit tests.
*/
int main(void)
{
struct ast_config ast_conf;
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS
};
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
/* Enable osc32 oscillator*/
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
/* Disable all AST wake enable bits for safety since the AST is reset
only by a POR. */
ast_enable(AST);
ast_conf.mode = AST_COUNTER_MODE;
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = AST_PSEL_32KHZ_1HZ;
ast_conf.counter = 0;
ast_set_config(AST, &ast_conf);
ast_disable_wakeup(AST, AST_WAKEUP_ALARM);
ast_disable_wakeup(AST, AST_WAKEUP_PER);
ast_disable_wakeup(AST, AST_WAKEUP_OVF);
ast_disable(AST);
/* Configurate the USART to board monitor */
bm_init();
/* Define all the test cases. */
DEFINE_TEST_CASE(picouart_test, NULL, run_picouart_test, NULL,
"SAM PICOUART wakeup test.");
DEFINE_TEST_CASE(getversion_test, NULL, run_getversion_test, NULL,
"SAM get version test.");
/* Put test case addresses in an array. */
DEFINE_TEST_ARRAY(picouart_tests) = {
&getversion_test,
&picouart_test,
};
/* Define the test suite. */
DEFINE_TEST_SUITE(picouart_suite, picouart_tests,
"SAM PICOUART driver test suite");
/* Run all tests in the test suite. */
test_suite_run(&picouart_suite);
while (1) {
/* Busy-wait forever. */
}
}
/**
* \brief Test Oscillator 0/1
*
* This test enables the oscillator 0 and 1 (if have), and then
* check if they can be stable and ready for main clock after
* startup time
*
* \param test Current test case.
*/
static void run_osc_test(const struct test_case *test)
{
volatile uint32_t wait;
bool status;
/* avoid Cppcheck Warning */
UNUSED(wait);
UNUSED(status);
#ifdef BOARD_OSC0_HZ
osc_enable(OSC_ID_OSC0);
for (wait =0; wait < OSC0_STARTUP_TIMEOUT; wait++) {
//waiting the oscillator0 stable
__asm__("nop");
};
status = osc_is_ready(OSC_ID_OSC0);
test_assert_true(test, status, "Oscillator 0 is not stable");
#endif
#ifdef BOARD_OSC1_HZ
osc_enable(OSC_ID_OSC1);
for (wait = 0; wait < OSC1_STARTUP_TIMEOUT; wait++) {
//waiting the oscillator1 stable
__asm__("nop");
};
status = osc_is_ready(OSC_ID_OSC1);
test_assert_true(test, status, "Oscillator 1 is not stable");
#endif
#ifdef BOARD_RC8M_HZ
osc_enable(OSC_ID_RC8M);
status = osc_is_ready(OSC_ID_RC8M);
test_assert_true(test, status, "8M/1M RC oscillator is not stable");
#endif
#ifdef BOARD_RC120_HZ
osc_enable(OSC_ID_RC120M);
status = osc_is_ready(OSC_ID_RC120M);
test_assert_true(test, status, "120M RC oscillator is not stable");
#endif
#ifdef BOARD_RC1M_HZ
osc_enable(OSC_ID_RC1M);
status = osc_is_ready(OSC_ID_RC1M);
test_assert_true(test, status, "1M RC oscillator is not stable");
#endif
#ifdef BOARD_RC80M_HZ
osc_enable(OSC_ID_RC80M);
status = osc_is_ready(OSC_ID_RC80M);
test_assert_true(test, status, "80M RC oscillator is not stable");
#endif
#ifdef BOARD_RCFAST_HZ
osc_enable(OSC_ID_RCFAST);
status = osc_is_ready(OSC_ID_RCFAST);
test_assert_true(test, status, "RCFAST oscillator is not stable");
#endif
}
/**
* \brief Enable clock for the USB module
*
* \pre CONFIG_USBCLK_SOURCE must be defined.
*
* \param frequency The required USB clock frequency in MHz:
* \arg \c 6 for 6 MHz
* \arg \c 48 for 48 MHz
*/
void sysclk_enable_usb(uint8_t frequency)
{
uint8_t prescaler;
Assert((frequency == 6) || (frequency == 48));
/*
* Enable or disable prescaler depending on if the USB frequency is 6
* MHz or 48 MHz. Only 6 MHz USB frequency requires prescaling.
*/
if (frequency == 6) {
prescaler = CLK_USBPSDIV_8_gc;
}
else {
prescaler = 0;
}
/*
* Switch to the system clock selected by the user.
*/
switch (CONFIG_USBCLK_SOURCE) {
case USBCLK_SRC_RCOSC:
if (!osc_is_ready(OSC_ID_RC32MHZ)) {
osc_enable(OSC_ID_RC32MHZ);
osc_wait_ready(OSC_ID_RC32MHZ);
#ifdef CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC
if (CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC
!= OSC_ID_USBSOF) {
osc_enable(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
osc_wait_ready(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
}
osc_enable_autocalibration(OSC_ID_RC32MHZ,
CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
#endif
}
ccp_write_io((uint8_t *)&CLK.USBCTRL, (prescaler)
| CLK_USBSRC_RC32M_gc
| CLK_USBSEN_bm);
break;
#ifdef CONFIG_PLL0_SOURCE
case USBCLK_SRC_PLL:
pll_enable_config_defaults(0);
ccp_write_io((uint8_t *)&CLK.USBCTRL, (prescaler)
| CLK_USBSRC_PLL_gc
| CLK_USBSEN_bm);
break;
#endif
default:
Assert(false);
break;
}
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_USB);
}
/* Override the default definition of vPortSetupTimerInterrupt() that is weakly
defined in the FreeRTOS Cortex-M3 port layer with a version that configures the
asynchronous timer (AST) to generate the tick interrupt. */
void vPortSetupTimerInterrupt( void )
{
struct ast_config ast_conf;
/* Ensure the AST can bring the CPU out of sleep mode. */
sleepmgr_lock_mode( SLEEPMGR_RET );
/* Ensure the 32KHz oscillator is enabled. */
if( osc_is_ready( OSC_ID_OSC32 ) == pdFALSE )
{
osc_enable( OSC_ID_OSC32 );
osc_wait_ready( OSC_ID_OSC32 );
}
/* Enable the AST itself. */
ast_enable( AST );
ast_conf.mode = AST_COUNTER_MODE; /* Simple up counter. */
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = 0; /* No prescale so the actual frequency is 32KHz/2. */
ast_conf.counter = 0;
ast_set_config( AST, &ast_conf );
/* The AST alarm interrupt is used as the tick interrupt. Ensure the alarm
status starts clear. */
ast_clear_interrupt_flag( AST, AST_INTERRUPT_ALARM );
/* Enable wakeup from alarm 0 in the AST and power manager. */
ast_enable_wakeup( AST, AST_WAKEUP_ALARM );
bpm_enable_wakeup_source( BPM, ( 1 << BPM_BKUPWEN_AST ) );
/* Tick interrupt MUST execute at the lowest interrupt priority. */
NVIC_SetPriority( AST_ALARM_IRQn, configLIBRARY_LOWEST_INTERRUPT_PRIORITY);
ast_enable_interrupt( AST, AST_INTERRUPT_ALARM );
NVIC_ClearPendingIRQ( AST_ALARM_IRQn );
NVIC_EnableIRQ( AST_ALARM_IRQn );
/* Automatically clear the counter on interrupt. */
ast_enable_counter_clear_on_alarm( AST, portAST_ALARM_CHANNEL );
/* Start with the tick active and generating a tick with regular period. */
ast_write_alarm0_value( AST, ulAlarmValueForOneTick );
ast_write_counter_value( AST, 0 );
/* See the comments where xMaximumPossibleSuppressedTicks is declared. */
xMaximumPossibleSuppressedTicks = ULONG_MAX / ulAlarmValueForOneTick;
}
/**
* \brief Test 32KHz oscillator
*
* This test enables the 32KHz oscillator, and then
* check if they can be used after startup time
*
* \param test Current test case.
*/
static void run_osc32_test(const struct test_case *test)
{
#ifdef BOARD_OSC32_HZ
uint32_t osc32_startup_timeout;
volatile uint32_t wait;
bool status;
osc_enable(OSC_ID_OSC32);
osc32_startup_timeout = OSC_RCSYS_NOMINAL_HZ/4;
// wait for 1s
for (wait = 0; wait < osc32_startup_timeout; wait++) {
//waiting the 32KHz oscillator ready
__asm__("nop");
};
status = osc_is_ready(OSC_ID_OSC32);
test_assert_true(test, status, "32KHz oscillator is not stable");
#endif
}
static void config_ast(void)
{
struct ast_config ast_conf;
/* Enable osc32 oscillator*/
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
/* Enable the AST */
ast_enable(AST);
ast_conf.mode = AST_COUNTER_MODE;
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = AST_PSEL_32KHZ_1HZ;
ast_conf.counter = 0;
/*
* Using counter mode and set it to 0.
* Initialize the AST.
*/
if (!ast_set_config(AST, &ast_conf)) {
printf("Error initializing the AST\r\n");
while (1) {
}
}
/* First clear alarm status. */
ast_clear_interrupt_flag(AST, AST_INTERRUPT_ALARM);
/* Enable wakeup from alarm0. */
ast_enable_wakeup(AST, AST_WAKEUP_ALARM);
/* Set callback for alarm0. */
ast_set_callback(AST, AST_INTERRUPT_ALARM, ast_alarm_callback,
AST_ALARM_IRQn, 1);
/* Disable first interrupt for alarm0. */
ast_disable_interrupt(AST, AST_INTERRUPT_ALARM);
}
/**
* \brief Run AST driver unit tests.
*/
int main(void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS
};
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
/* Enable osc32 oscillator*/
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
/* Define all the test cases. */
DEFINE_TEST_CASE(alarm_test, NULL, run_alarm_test, NULL,
"SAM AST alarm interrupt and wakeup test.");
DEFINE_TEST_CASE(periodic_test, NULL, run_periodic_test, NULL,
"SAM AST periodic interrupt and wakeup test.");
/* Put test case addresses in an array. */
DEFINE_TEST_ARRAY(ast_tests) = {
&alarm_test,
&periodic_test,
};
/* Define the test suite. */
DEFINE_TEST_SUITE(ast_suite, ast_tests, "SAM AST driver test suite");
/* Run all tests in the test suite. */
test_suite_run(&ast_suite);
while (1) {
/* Busy-wait forever. */
}
}
/**
* \brief main function : do init and loop
*/
int main(void)
{
/* Initialize the SAM system */
sysclk_init();
board_init();
/* Initialize the console uart */
configure_console();
/* Output example information */
printf("-- AST Example 1 in Calendar Mode --\r\n");
printf("-- %s\n\r", BOARD_NAME);
printf("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
printf("Config AST with 32 KHz oscillator.\r\n");
/* Enable osc32 oscillator*/
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
struct ast_calendar calendar;
calendar.FIELD.sec = 0;
calendar.FIELD.min = 15;
calendar.FIELD.hour = 12;
calendar.FIELD.day = 20;
calendar.FIELD.month = 9;
calendar.FIELD.year = 14;
/* Enable the AST */
ast_enable(AST);
struct ast_config ast_conf;
ast_conf.mode = AST_CALENDAR_MODE;
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = AST_PSEL_32KHZ_1HZ;
ast_conf.calendar = calendar;
/* Initialize the AST */
if (!ast_set_config(AST, &ast_conf)) {
printf("Error initializing the AST\r\n");
while (1) {
}
}
while (1) {
/* slow down operations */
delay_s(1);
ioport_toggle_pin_level(LED0_GPIO);
/* Output the calendar */
calendar = ast_read_calendar_value(AST);
printf("\r");
printf("Calendar: Year:%02u Month:%02u Day:%02u, %02uh%02um%02us ",
(unsigned int)calendar.FIELD.year,
(unsigned int)calendar.FIELD.month,
(unsigned int)calendar.FIELD.day,
(unsigned int)calendar.FIELD.hour,
(unsigned int)calendar.FIELD.min,
(unsigned int)calendar.FIELD.sec);
}
}
/**
* \brief Run BPM driver unit tests.
*/
int main(void)
{
struct ast_config ast_conf;
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS
};
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
/* Initialize AST for all tests */
/* Enable osc32 oscillator*/
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
/* Enable the AST. */
ast_enable(AST);
ast_conf.mode = AST_COUNTER_MODE;
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = AST_PSEL_32KHZ_1HZ;
ast_conf.counter = 0;
ast_set_config(AST, &ast_conf);
/* Set periodic 0 to interrupt after 1/16 second in counter mode. */
ast_clear_interrupt_flag(AST, AST_INTERRUPT_PER);
ast_write_periodic0_value(AST, AST_PSEL_32KHZ_1HZ - 2);
ast_set_callback(AST, AST_INTERRUPT_PER, ast_per_callback,
AST_PER_IRQn, 1);
ast_enable_wakeup(AST, AST_WAKEUP_PER);
/* AST can wakeup the device */
bpm_enable_wakeup_source(BPM, (1 << BPM_BKUPWEN_AST));
/**
* Retain I/O lines after wakeup from backup.
* Disable to undo the previous retention state then enable.
*/
bpm_disable_io_retention(BPM);
bpm_enable_io_retention(BPM);
/* Enable fast wakeup */
bpm_enable_fast_wakeup(BPM);
/* Define all the test cases. */
DEFINE_TEST_CASE(backup_test, NULL, run_backup_test, NULL,
"Backup Power Manager, Backup mode & wakeup.");
DEFINE_TEST_CASE(ps_test, NULL, run_ps_test, NULL,
"Backup Power Manager, Power Scaling.");
DEFINE_TEST_CASE(ret_test, NULL, run_ret_test, NULL,
"Backup Power Manager, Retention mode & wakeup.");
DEFINE_TEST_CASE(wait_test, NULL, run_wait_test, NULL,
"Backup Power Manager, Wait mode & wakeup.");
DEFINE_TEST_CASE(sleep_3_test, NULL, run_sleep_3_test, NULL,
"Backup Power Manager, Sleep mode 3 & wakeup.");
DEFINE_TEST_CASE(sleep_2_test, NULL, run_sleep_2_test, NULL,
"Backup Power Manager, Sleep mode 2 & wakeup.");
DEFINE_TEST_CASE(sleep_1_test, NULL, run_sleep_1_test, NULL,
"Backup Power Manager, Sleep mode 1 & wakeup.");
DEFINE_TEST_CASE(sleep_0_test, NULL, run_sleep_0_test, NULL,
"Backup Power Manager, Sleep mode 0 & wakeup.");
/* Put test case addresses in an array. */
DEFINE_TEST_ARRAY(bpm_tests) = {
&backup_test,
&ps_test,
&ret_test,
&wait_test,
&sleep_3_test,
&sleep_2_test,
&sleep_1_test,
&sleep_0_test,
};
/* Define the test suite. */
DEFINE_TEST_SUITE(bpm_suite, bpm_tests, "SAM BPM driver test suite");
/* Run all tests in the test suite. */
test_suite_run(&bpm_suite);
/* Disable the AST */
ast_disable(AST);
while (1) {
/* Busy-wait forever. */
}
}
/**
* \brief Test watchdog for all cases.
*
* \note Because MCU will be reset serval times druing the test,
* to simplify the design, only one test case but with many test stages.
*
* \param test Current test case.
*/
static void run_wdt_test_all(const struct test_case *test)
{
struct wdt_dev_inst wdt_inst;
struct wdt_config wdt_cfg;
uint32_t wdt_window_ms = 0;
uint32_t wdt_timeout_ms = 0;
uint32_t wdt_ut_stage;
/* Get test stage */
wdt_ut_stage = (uint32_t)(*(uint32_t *)WDT_UT_TAG_ADDR);
if (is_wdt_reset()) {
/* Check if the reset is as expected */
switch (wdt_ut_stage) {
case WDT_UT_STAGE_START:
test_assert_true(test, 0,
"Unexpected watchdog reset at start stage!");
break;
case WDT_UT_STAGE_RST_MCU:
/* Move to next stage */
wdt_ut_stage = WDT_UT_STAGE_BM_NORMAL;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
break;
case WDT_UT_STAGE_BM_NORMAL:
test_assert_true(test, 0,
"Unexpected watchdog reset at basic mode!");
break;
case WDT_UT_STAGE_BM_TIMEOUT_RST:
/* Move to next stage */
wdt_ut_stage = WDT_UT_STAGE_WM_NORMAL;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
break;
case WDT_UT_STAGE_WM_NORMAL:
test_assert_true(test, 0,
"Unexpected watchdog reset at window mode!");
break;
case WDT_UT_STAGE_WM_TIMEBAN_RST:
/* Move to next stage */
wdt_ut_stage = WDT_UT_STAGE_WM_TIMEOUT_RST;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
break;
case WDT_UT_STAGE_WM_TIMEOUT_RST:
/* Move to next stage */
wdt_ut_stage = WDT_UT_STAGE_END;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
break;
case WDT_UT_STAGE_END:
test_assert_true(test, 0,
"Unexpected watchdog reset at end stage!");
break;
default:
test_assert_true(test, 0,
"Unexpected watchdog reset!");
break;
}
} else {
/* First WDT unit test start at here, set stage flag */
wdt_ut_stage = WDT_UT_STAGE_START;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
}
/*
* ---- Test reset MCU by the WDT ----
*/
if (wdt_ut_stage == WDT_UT_STAGE_START) {
bool ret;
/* Move to next stage */
wdt_ut_stage = WDT_UT_STAGE_RST_MCU;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
/* Reset MCU by the watchdog. */
ret = wdt_reset_mcu();
test_assert_false(test, ret,
"Can't reset MCU by the WDT: failed!");
/* The code should not go to here */
test_assert_true(test, 0,
"Reset MCU by the WDT: failed!");
}
/*
* ---- Test the WDT in basic mode ----
*/
if ((wdt_ut_stage & WDT_UT_STAGE_MASK) == WDT_UT_STAGE_BM) {
/*
* Intialize the watchdog in basic mode:
* - Use default configuration.
* - But change timeout period to 0.57s
* (Ttimeout = 2pow(PSEL+1) / Fclk_cnt = 65535 / 115000).
*/
wdt_get_config_defaults(&wdt_cfg);
wdt_cfg.timeout_period = WDT_PERIOD_65536_CLK;
wdt_timeout_ms = 570;
wdt_init(&wdt_inst, WDT, &wdt_cfg);
wdt_enable(&wdt_inst);
wdt_clear(&wdt_inst);
mdelay(wdt_timeout_ms / 2);
wdt_clear(&wdt_inst);
/* The code should reach here */
test_assert_true(test, 1,
"Clear the WDT in basic mode: passed.");
/* Move to next stage */
wdt_ut_stage = WDT_UT_STAGE_BM_TIMEOUT_RST;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
/* Wait for the WDT reset */
mdelay(wdt_timeout_ms * 2);
/* The code should not go to here, disable watchdog for default */
wdt_disable(&wdt_inst);
test_assert_true(test, 0,
"No WDT reset happened in basic mode!");
}
/*
* ---- Test the WDT in window mode ----
*/
if ((wdt_ut_stage & WDT_UT_STAGE_MASK) == WDT_UT_STAGE_WM) {
/* Enable WDT clock source if need */
if (BPM->BPM_PMCON & BPM_PMCON_CK32S) {
/* Enable 32K RC oscillator */
if (!osc_is_ready(OSC_ID_RC32K)) {
osc_enable(OSC_ID_RC32K);
osc_wait_ready(OSC_ID_RC32K);
}
} else {
/* Enable external OSC32 oscillator */
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
}
/*
* Intialize the watchdog in window mode:
* - Use 32K oscillator as WDT clock source.
* - Set timeout/timeban period to 0.5s
* (Ttimeout = 2pow(PSEL+1) / Fclk_cnt = 16384 / 32768).
*/
wdt_get_config_defaults(&wdt_cfg);
wdt_cfg.wdt_mode = WDT_MODE_WINDOW;
wdt_cfg.clk_src = WDT_CLK_SRC_32K;
wdt_cfg.window_period = WDT_PERIOD_16384_CLK;
wdt_cfg.timeout_period = WDT_PERIOD_16384_CLK;
wdt_window_ms = 500;
wdt_timeout_ms = 500;
wdt_init(&wdt_inst, WDT, &wdt_cfg);
wdt_enable(&wdt_inst);
mdelay(wdt_window_ms + wdt_timeout_ms / 10);
wdt_clear(&wdt_inst);
/* The code should reach here */
test_assert_true(test, 1,
"Clear the WDT in window mode: passed.");
if (wdt_ut_stage == WDT_UT_STAGE_WM_NORMAL) {
/* Move to next stage */
wdt_ut_stage = WDT_UT_STAGE_WM_TIMEBAN_RST;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
/* Clear the WDT in time ban window */
wdt_clear(&wdt_inst);
/* The WDT reset should happen */
mdelay(50);
} else if (wdt_ut_stage == WDT_UT_STAGE_WM_TIMEOUT_RST) {
/* Wait for the WDT reset when timeout */
mdelay(wdt_window_ms);
mdelay(wdt_timeout_ms * 2);
}
/* The code should not go to here, disable watchdog for default */
wdt_disable(&wdt_inst);
test_assert_true(test, 0,
"No WDT reset happened in window mode!");
}
/*
* ---- Check if all test are OK ----
*/
if (wdt_ut_stage == WDT_UT_STAGE_END) {
test_assert_true(test, 1,
"All test stages done for WDT.");
/* Clear flash content */
wdt_ut_stage = 0xFFFFFFFFu;
flashcalw_memcpy((void *)WDT_UT_TAG_ADDR, &wdt_ut_stage, 4, true);
} else {
test_assert_true(test, 0,
"WDT test stopped with unexpected stages.");
}
}
/*!
* \brief main function : do init and loop (poll if configured so)
*/
int main(void)
{
uint8_t key;
struct picouart_dev_inst dev_inst;
struct picouart_config config;
struct ast_config ast_conf;
/* Initialize the SAM system */
sysclk_init();
board_init();
/* Initialize the console uart */
configure_console();
/* Output example information */
printf("\r\n");
printf("-- PICOUART Example 1 --\r\n");
printf("-- %s\r\n", BOARD_NAME);
printf("-- Compiled: %s %s --\r\n", __DATE__, __TIME__);
printf("-- IMPORTANT: This example requires a board "
"monitor firmware version V1.3 or greater.\r\n");
/* Enable osc32 oscillator*/
if (!osc_is_ready(OSC_ID_OSC32)) {
osc_enable(OSC_ID_OSC32);
osc_wait_ready(OSC_ID_OSC32);
}
/* Disable all AST wake enable bits for safety since the AST is reset
only by a POR. */
ast_enable(AST);
ast_conf.mode = AST_COUNTER_MODE;
ast_conf.osc_type = AST_OSC_32KHZ;
ast_conf.psel = AST_PSEL_32KHZ_1HZ;
ast_conf.counter = 0;
ast_set_config(AST, &ast_conf);
ast_disable_wakeup(AST, AST_WAKEUP_ALARM);
ast_disable_wakeup(AST, AST_WAKEUP_PER);
ast_disable_wakeup(AST, AST_WAKEUP_OVF);
ast_disable(AST);
/* Config the push button */
config_buttons();
/* Configurate the USART to board monitor */
bm_init();
sysclk_enable_hsb_module(SYSCLK_PBA_BRIDGE);
sysclk_enable_peripheral_clock(BM_USART_USART);
/* Init the PICOUART */
picouart_get_config_defaults(&config);
picouart_init(&dev_inst, PICOUART, &config);
/* Enable the PICOUART */
picouart_enable(&dev_inst);
/* PICOUART and EIC can wakeup the device */
config_wakeup();
/* Display menu */
display_menu();
while (1) {
scanf("%c", (char *)&key);
switch (key) {
case 'h':
display_menu();
break;
case 's':
if (bm_flag) {
printf("Switch off the board monitor to wake up..\r\n");
bm_flag = false;
} else {
printf("Switch on the board monitor to wake up..\r\n");
bm_flag = true;
}
break;
case '0':
printf("Enter Sleep mode with start bit wakeup.\r\n");
config.action = PICOUART_ACTION_WAKEUP_ON_STARTBIT;
picouart_set_config(&dev_inst, &config);
if (bm_flag) {
printf("Board monitor will send frame after 3 seconds.\r\n");
bm_send_picouart_frame('A', 3000);
}
/* Wait for the printf operation to finish before
setting the device in a power save mode. */
delay_ms(30);
bpm_sleep(BPM, BPM_SM_SLEEP_2);
printf("--Exit Sleep mode.\r\n\r\n");
break;
case '1':
printf("Enter Retention mode with full frame wakeup.\r\n");
config.action = PICOUART_ACTION_WAKEUP_ON_FULLFRAME;
picouart_set_config(&dev_inst, &config);
if (bm_flag) {
printf("Board monitor will send frame after 3 seconds.\r\n");
bm_send_picouart_frame('T', 3000);
}
/* Wait for the printf operation to finish before
setting the device in a power save mode. */
delay_ms(30);
bpm_sleep(BPM, BPM_SM_RET);
printf("--Exit Retention mode.\r\n\r\n");
break;
case '2':
printf("Enter backup mode with character match wakeup.\r\n");
config.action = PICOUART_ACTION_WAKEUP_ON_MATCH;
config.match = 'L';
picouart_set_config(&dev_inst, &config);
if (bm_flag) {
printf("Board monitor will send frame after 3 seconds.\r\n");
bm_send_picouart_frame('L', 3000);
}
/* Wait for the printf operation to finish before
setting the device in a power save mode. */
delay_ms(30);
bpm_sleep(BPM, BPM_SM_BACKUP);
break;
default:
break;
}
}
}
