//!
//! \return none
//!
//! \brief Initializes Push Button Ports and Pins
//
//*****************************************************************************
void Button_IF_Init(P_INT_HANDLER S2InterruptHdl,P_INT_HANDLER S3InterruptHdl )
{
//
// Set Interrupt Type for GPIO
//
MAP_GPIOIntTypeSet(GPIOA1_BASE,GPIO_PIN_5,GPIO_FALLING_EDGE);
MAP_GPIOIntTypeSet(GPIOA2_BASE,GPIO_PIN_6,GPIO_FALLING_EDGE);
g_S3InterruptHdl = S3InterruptHdl;
g_S2InterruptHdl = S2InterruptHdl;
//
// Register Interrupt handler
//
osi_InterruptRegister(INT_GPIOA1,(P_OSI_INTR_ENTRY)GPIOs3IntHandler, INT_PRIORITY_LVL_1);
osi_InterruptRegister(INT_GPIOA2,(P_OSI_INTR_ENTRY)GPIOs2IntHandler, INT_PRIORITY_LVL_1);
//
// Enable Interrupt
//
MAP_GPIOIntClear(GPIOA1_BASE,GPIO_PIN_5);
MAP_GPIOIntEnable(GPIOA1_BASE,GPIO_INT_PIN_5);
MAP_GPIOIntClear(GPIOA2_BASE,GPIO_PIN_6);
MAP_GPIOIntEnable(GPIOA2_BASE,GPIO_INT_PIN_6);
}
int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) //do not know what to do with pValue
{
if(InterruptHdl == NULL)
{
//De-register Interprocessor communication interrupt between App and NWP
#ifdef SL_PLATFORM_MULTI_THREADED
osi_InterruptDeRegister(INT_NWPIC);
#else
IntDisable(INT_NWPIC);
IntUnregister(INT_NWPIC);
IntPendClear(INT_NWPIC);
#endif
g_pHostIntHdl = NULL;
}
else
{
g_pHostIntHdl = InterruptHdl;
#if 0
//Setting the 14th and 13th bit to '01' to make the HOST_IRQ edge triggered
HWREG(0x4402E168) |= 0x2000;
#endif
#ifdef SL_PLATFORM_MULTI_THREADED
IntPendClear(INT_NWPIC);
osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)HostIntHanlder,INT_PRIORITY_LVL_1);
#else
IntRegister(INT_NWPIC, HostIntHanlder);
IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1);
IntPendClear(INT_NWPIC);
IntEnable(INT_NWPIC);
#endif
}
return 0;
}
int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) //do not know what to do with pValue
{
if(InterruptHdl == NULL)
{
//De-register Interprocessor communication interrupt between App and NWP
#ifdef SL_PLATFORM_MULTI_THREADED
osi_InterruptDeRegister(INT_NWPIC);
#else
MAP_IntDisable(INT_NWPIC);
MAP_IntUnregister(INT_NWPIC);
MAP_IntPendClear(INT_NWPIC);
#endif
}
else
{
#ifdef SL_PLATFORM_MULTI_THREADED
MAP_IntPendClear(INT_NWPIC);
osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)InterruptHdl,
INT_PRIORITY_LVL_1);
#else
MAP_IntRegister(INT_NWPIC, InterruptHdl);
MAP_IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1);
MAP_IntPendClear(INT_NWPIC);
MAP_IntEnable(INT_NWPIC);
#endif
}
return 0;
}
//****************************************************************************
//
//! Configures the GPIO selected as input to generate interrupt on activity
//!
//! \param uiGPIOPort is the GPIO port address
//! \param ucGPIOPin is the GPIO pin of the specified port
//! \param uiIntType is the type of the interrupt (refer gpio.h)
//! \param pfnIntHandler is the interrupt handler to register
//!
//! This function
//! 1. Sets GPIO interrupt type
//! 2. Registers Interrupt handler
//! 3. Enables Interrupt
//!
//! \return None
//
//****************************************************************************
void
GPIO_IF_ConfigureNIntEnable(unsigned int uiGPIOPort,
unsigned char ucGPIOPin,
unsigned int uiIntType,
void (*pfnIntHandler)(void))
{
//
// Set GPIO interrupt type
//
MAP_GPIOIntTypeSet(uiGPIOPort,ucGPIOPin,uiIntType);
//
// Register Interrupt handler
//
#if defined(USE_TIRTOS) || defined(USE_FREERTOS) || defined(SL_PLATFORM_MULTI_THREADED)
// USE_TIRTOS: if app uses TI-RTOS (either networking/non-networking)
// USE_FREERTOS: if app uses Free-RTOS (either networking/non-networking)
// SL_PLATFORM_MULTI_THREADED: if app uses any OS + networking(simplelink)
osi_InterruptRegister(GetPeripheralIntNum(uiGPIOPort),
pfnIntHandler, INT_PRIORITY_LVL_1);
#else
MAP_IntPrioritySet(GetPeripheralIntNum(uiGPIOPort), INT_PRIORITY_LVL_1);
MAP_GPIOIntRegister(uiGPIOPort,pfnIntHandler);
#endif
//
// Enable Interrupt
//
MAP_GPIOIntClear(uiGPIOPort,ucGPIOPin);
MAP_GPIOIntEnable(uiGPIOPort,ucGPIOPin);
}
//****************************************************************************
//
//! Initialize the watchdog timer
//!
//! \param fpAppWDTCB is the WDT interrupt handler to be registered
//! \param uiReloadVal is the reload value to be set to the WDT
//!
//! This function
//! 1. Initializes the WDT
//!
//! \return None.
//
//****************************************************************************
void WDT_IF_Init(fAPPWDTDevCallbk fpAppWDTCB,
unsigned int uiReloadVal)
{
//
// Enable the peripherals used by this example.
//
MAP_PRCMPeripheralClkEnable(PRCM_WDT, PRCM_RUN_MODE_CLK);
//
// Unlock to be able to configure the registers
//
MAP_WatchdogUnlock(WDT_BASE);
if(fpAppWDTCB != NULL)
{
#ifdef USE_TIRTOS
osi_InterruptRegister(INT_WDT, fpAppWDTCB, INT_PRIORITY_LVL_1);
#else
MAP_WatchdogIntRegister(WDT_BASE,fpAppWDTCB);
#endif
}
//
// Set the watchdog timer reload value
//
MAP_WatchdogReloadSet(WDT_BASE,uiReloadVal);
//
// Start the timer. Once the timer is started, it cannot be disable.
//
MAP_WatchdogEnable(WDT_BASE);
}
//****************************************************************************
//
//! Configures the GPIO selected as input to generate interrupt on activity
//!
//! \param uiGPIOPort is the GPIO port address
//! \param ucGPIOPin is the GPIO pin of the specified port
//! \param uiIntType is the type of the interrupt (refer gpio.h)
//! \param pfnIntHandler is the interrupt handler to register
//!
//! This function
//! 1. Sets GPIO interrupt type
//! 2. Registers Interrupt handler
//! 3. Enables Interrupt
//!
//! \return None
//
//****************************************************************************
void
GPIO_IF_ConfigureNIntEnable(unsigned int uiGPIOPort,
unsigned char ucGPIOPin,
unsigned int uiIntType,
void (*pfnIntHandler)(void))
{
//
// Set GPIO interrupt type
//
MAP_GPIOIntTypeSet(uiGPIOPort,ucGPIOPin,uiIntType);
//
// Register Interrupt handler
//
#ifdef USE_TIRTOS
osi_InterruptRegister(GetPeripheralIntNum(uiGPIOPort),
pfnIntHandler, INT_PRIORITY_LVL_1);
#else
MAP_GPIOIntRegister(uiGPIOPort,pfnIntHandler);
#endif
//
// Enable Interrupt
//
MAP_GPIOIntClear(uiGPIOPort,ucGPIOPin);
MAP_GPIOIntEnable(uiGPIOPort,ucGPIOPin);
}
//*****************************************************************************
//
//! Initialize the DMA controller
//!
//! \param None
//!
//! This function initializes
//! 1. Initializes the McASP module
//!
//! \return None.
//
//*****************************************************************************
void UDMAInit()
{
unsigned int uiLoopCnt;
//
// Enable McASP at the PRCM module
//
MAP_PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralReset(PRCM_UDMA);
//
// Register interrupt handlers
//
#if defined(USE_TIRTOS) || defined(USE_FREERTOS) || defined(SL_PLATFORM_MULTI_THREADED)
// USE_TIRTOS: if app uses TI-RTOS (either networking/non-networking)
// USE_FREERTOS: if app uses Free-RTOS (either networking/non-networking)
// SL_PLATFORM_MULTI_THREADED: if app uses any OS + networking(simplelink)
osi_InterruptRegister(INT_UDMA, DmaSwIntHandler, INT_PRIORITY_LVL_1);
osi_InterruptRegister(INT_UDMAERR, DmaErrorIntHandler, INT_PRIORITY_LVL_1);
#else
MAP_IntPrioritySet(INT_UDMA, INT_PRIORITY_LVL_1);
MAP_uDMAIntRegister(UDMA_INT_SW, DmaSwIntHandler);
MAP_IntPrioritySet(INT_UDMAERR, INT_PRIORITY_LVL_1);
MAP_uDMAIntRegister(UDMA_INT_ERR, DmaErrorIntHandler);
#endif
//
// Enable uDMA using master enable
//
MAP_uDMAEnable();
//
// Set Control Table
//
memset(gpCtlTbl,0,sizeof(tDMAControlTable)*CTL_TBL_SIZE);
MAP_uDMAControlBaseSet(gpCtlTbl);
//
// Reset App Callbacks
//
for(uiLoopCnt = 0; uiLoopCnt < MAX_NUM_CH; uiLoopCnt++)
{
gfpAppCallbackHndl[uiLoopCnt] = NULL;
}
}
//*****************************************************************************
//
//! setting up the timer
//!
//! \param ulBase is the base address for the timer.
//! \param ulTimer selects between the TIMER_A or TIMER_B or TIMER_BOTH.
//! \param TimerBaseIntHandler is the pointer to the function that handles the
//! interrupt for the Timer
//!
//! This function
//! 1. Register the function handler for the timer interrupt.
//! 2. enables the timer interrupt.
//!
//! \return none
//
//*****************************************************************************
void Timer_IF_IntSetup(unsigned long ulBase, unsigned long ulTimer,
void (*TimerBaseIntHandler)(void))
{
//
// Setup the interrupts for the timer timeouts.
//
#if defined(USE_TIRTOS) || defined(USE_FREERTOS) || defined(SL_PLATFORM_MULTI_THREADED)
// USE_TIRTOS: if app uses TI-RTOS (either networking/non-networking)
// USE_FREERTOS: if app uses Free-RTOS (either networking/non-networking)
// SL_PLATFORM_MULTI_THREADED: if app uses any OS + networking(simplelink)
if(ulTimer == TIMER_BOTH)
{
osi_InterruptRegister(GetPeripheralIntNum(ulBase, TIMER_A),
TimerBaseIntHandler, INT_PRIORITY_LVL_1);
osi_InterruptRegister(GetPeripheralIntNum(ulBase, TIMER_B),
TimerBaseIntHandler, INT_PRIORITY_LVL_1);
}
else
{
osi_InterruptRegister(GetPeripheralIntNum(ulBase, ulTimer),
TimerBaseIntHandler, INT_PRIORITY_LVL_1);
}
#else
MAP_IntPrioritySet(GetPeripheralIntNum(ulBase, ulTimer), INT_PRIORITY_LVL_1);
MAP_TimerIntRegister(ulBase, ulTimer, TimerBaseIntHandler);
#endif
if(ulTimer == TIMER_BOTH)
{
MAP_TimerIntEnable(ulBase, TIMER_TIMA_TIMEOUT|TIMER_TIMB_TIMEOUT);
}
else
{
MAP_TimerIntEnable(ulBase, ((ulTimer == TIMER_A) ? TIMER_TIMA_TIMEOUT :
TIMER_TIMB_TIMEOUT));
}
}
void pyb_sleep_init0 (void) {
// initialize the sleep objects list
mp_obj_list_init(&MP_STATE_PORT(pyb_sleep_obj_list), 0);
// register and enable the PRCM interrupt
osi_InterruptRegister(INT_PRCM, (P_OSI_INTR_ENTRY)PRCMInterruptHandler, INT_PRIORITY_LVL_1);
// disable all LPDS and hibernate wake up sources (WLAN is disabed/enabled before entering LDPS mode)
MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_GPIO);
MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_TIMER);
MAP_PRCMHibernateWakeupSourceDisable(PRCM_HIB_SLOW_CLK_CTR | PRCM_HIB_GPIO2 | PRCM_HIB_GPIO4 | PRCM_HIB_GPIO13 |
PRCM_HIB_GPIO17 | PRCM_HIB_GPIO11 | PRCM_HIB_GPIO24 | PRCM_HIB_GPIO26);
// check the reset casue (if it's soft reset, leave it as it is)
if (pybsleep_reset_cause != PYB_SLP_SOFT_RESET) {
switch (MAP_PRCMSysResetCauseGet()) {
case PRCM_POWER_ON:
pybsleep_reset_cause = PYB_SLP_PWRON_RESET;
break;
case PRCM_CORE_RESET:
case PRCM_MCU_RESET:
case PRCM_SOC_RESET:
pybsleep_reset_cause = PYB_SLP_HARD_RESET;
break;
case PRCM_WDT_RESET:
pybsleep_reset_cause = PYB_SLP_WDT_RESET;
break;
case PRCM_HIB_EXIT:
if (PRCMGetSpecialBit(PRCM_WDT_RESET_BIT)) {
pybsleep_reset_cause = PYB_SLP_WDT_RESET;
}
else {
pybsleep_reset_cause = PYB_SLP_HIB_RESET;
// set the correct wake reason
switch (MAP_PRCMHibernateWakeupCauseGet()) {
case PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK:
pybsleep_wake_reason = PYB_SLP_WAKED_BY_RTC;
// TODO repeat the alarm
break;
case PRCM_HIB_WAKEUP_CAUSE_GPIO:
pybsleep_wake_reason = PYB_SLP_WAKED_BY_GPIO;
break;
default:
break;
}
}
break;
default:
break;
}
}
}
static void EmitCtrlInit(void)
{
s_ulTimerEmitCtrl = TIMERA1_BASE;
MAP_PRCMPeripheralClkEnable(PRCM_TIMERA1,PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralReset(PRCM_TIMERA1);
MAP_TimerConfigure(s_ulTimerEmitCtrl,TIMER_CFG_PERIODIC);
MAP_TimerPrescaleSet(s_ulTimerEmitCtrl,TIMER_A,0);
//MAP_TimerIntRegister(s_ulTimerEmitCtrl,TIMER_A,TimerEmitCtrlHandler);
osi_InterruptRegister(INT_TIMERA1A, TimerEmitCtrlHandler, 32);
MAP_TimerIntEnable(s_ulTimerEmitCtrl,TIMER_TIMA_TIMEOUT);
}
void SampleInit(void)
{
/*
//UDMAInit();
// Reset SPI
//MAP_SPIReset(GSPI_BASE);
MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3,
(SPI_HW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_ON|
SPI_CS_ACTIVELOW |
SPI_WL_8));
MAP_SPIEnable(GSPI_BASE);
MAP_SPICSEnable(GSPI_BASE);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO);
SPIFIFOLevelSet(GSPI_BASE,1,1);
MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX|SPI_INT_DMATX);
//MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX);
//MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler);
osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32);
*/
UDMAInit();
MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3,
(SPI_HW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_ON|
SPI_CS_ACTIVEHIGH |
SPI_WL_8));
MAP_SPIEnable(GSPI_BASE);
MAP_SPICSEnable(GSPI_BASE);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO);
SPIFIFOLevelSet(GSPI_BASE,1,1);
MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX);
//MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX);
//MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler);
osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32);
}
//!
//! \return 0 - Success
//! -1 - Error
//!
//! \brief Initializes Audio Player Push Button Controls
//
//*****************************************************************************
long InitControl(P_AUDIO_HANDLER pAudioInControl,P_AUDIO_HANDLER pAudioOutControl)
{
long lRetVal = -1;
//
// Set Interrupt Type for GPIO
//
MAP_GPIOIntTypeSet(GPIOA1_BASE,GPIO_PIN_5,GPIO_FALLING_EDGE);
MAP_GPIOIntTypeSet(GPIOA2_BASE,GPIO_PIN_6,GPIO_FALLING_EDGE);
//
// Store Interrupt handlers
//
g_pAudioInControlHdl = pAudioInControl;
g_pAudioOutControlHdl = pAudioOutControl;
//
// Register Interrupt handler
//
lRetVal = osi_InterruptRegister(INT_GPIOA1,(P_OSI_INTR_ENTRY)MICButtonHandler,\
INT_PRIORITY_LVL_1);
ASSERT_ON_ERROR(lRetVal);
lRetVal = osi_InterruptRegister(INT_GPIOA2,(P_OSI_INTR_ENTRY) \
SpeakerButtonHandler,INT_PRIORITY_LVL_1);
ASSERT_ON_ERROR(lRetVal);
//
// Enable Interrupt
//
MAP_GPIOIntClear(GPIOA1_BASE,GPIO_PIN_5);
MAP_GPIOIntEnable(GPIOA1_BASE,GPIO_INT_PIN_5);
MAP_GPIOIntClear(GPIOA2_BASE,GPIO_PIN_6);
MAP_GPIOIntEnable(GPIOA2_BASE,GPIO_INT_PIN_6);
return SUCCESS;
}
//*****************************************************************************
//
//! Initialize the DMA controller
//!
//! \param None
//!
//! This function initializes
//! 1. Initializes the McASP module
//!
//! \return None.
//
//*****************************************************************************
void UDMAInit()
{
unsigned int uiLoopCnt;
//
// Enable McASP at the PRCM module
//
MAP_PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralReset(PRCM_UDMA);
//
// Register interrupt handlers
//
#ifdef USE_TIRTOS
osi_InterruptRegister(INT_UDMA, DmaSwIntHandler, INT_PRIORITY_LVL_1);
osi_InterruptRegister(INT_UDMAERR, DmaErrorIntHandler, INT_PRIORITY_LVL_1);
#else
MAP_uDMAIntRegister(UDMA_INT_SW, DmaSwIntHandler);
MAP_uDMAIntRegister(UDMA_INT_ERR, DmaErrorIntHandler);
#endif
//
// Enable uDMA using master enable
//
MAP_uDMAEnable();
//
// Set Control Table
//
memset(gpCtlTbl,0,sizeof(tDMAControlTable)*CTL_TBL_SIZE);
MAP_uDMAControlBaseSet(gpCtlTbl);
//
// Reset App Callbacks
//
for(uiLoopCnt = 0; uiLoopCnt < MAX_NUM_CH; uiLoopCnt++)
{
gfpAppCallbackHndl[uiLoopCnt] = NULL;
}
}
i32 register_isr(u8 irqvec_id,
void (*intr_handler)(void *),
void *param)
{
/* Setup the ISR handler list to be used to invoke on interrupt
occurance. The new setting will override the older ones always */
isr_handler_list[irqvec_id].reg_intr_handler = intr_handler;
isr_handler_list[irqvec_id].intr_param = param;
osi_InterruptRegister(irqvec_id, (P_OSI_INTR_ENTRY)global_intr_handler, (1 << 5));
if(INT_PRCM == irqvec_id) {
MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR);
}
return 0;
}
static void uart_int() {
int c = UARTCharGet(CONSOLE_UART);
struct prompt_event pe = {.type = PROMPT_CHAR_EVENT, .data = (void *) c};
osi_MsgQWrite(&s_v7_q, &pe, OSI_NO_WAIT);
MAP_UARTIntClear(CONSOLE_UART, UART_INT_RX);
}
void sj_prompt_init_hal(struct v7 *v7) {
(void) v7;
}
static void v7_task(void *arg) {
struct v7 *v7 = s_v7;
printf("\n\nSmart.JS for CC3200\n");
osi_MsgQCreate(&s_v7_q, "V7", sizeof(struct prompt_event), 32 /* len */);
osi_InterruptRegister(CONSOLE_UART_INT, uart_int, INT_PRIORITY_LVL_1);
MAP_UARTIntEnable(CONSOLE_UART, UART_INT_RX);
sl_Start(NULL, NULL, NULL);
v7 = s_v7 = init_v7(&v7);
sj_timers_api_setup(v7);
sj_v7_ext_api_setup(v7);
sj_init_sys(v7);
init_wifi(v7);
if (init_fs(v7) != 0) {
fprintf(stderr, "FS initialization failed.\n");
}
mongoose_init();
sj_http_api_setup(v7);
sj_i2c_api_setup(v7);
/* Common config infrastructure. Mongoose & v7 must be initialized. */
init_device(v7);
v7_val_t res;
if (v7_exec_file(v7, "sys_init.js", &res) != V7_OK) {
fprintf(stderr, "Error: ");
v7_fprint(stderr, v7, res);
}
sj_prompt_init(v7);
while (1) {
struct prompt_event pe;
mongoose_poll(MONGOOSE_POLL_LENGTH_MS);
if (osi_MsgQRead(&s_v7_q, &pe, V7_POLL_LENGTH_MS) != OSI_OK) continue;
switch (pe.type) {
case PROMPT_CHAR_EVENT: {
sj_prompt_process_char((char) ((int) pe.data));
break;
}
case V7_INVOKE_EVENT: {
struct v7_invoke_event_data *ied =
(struct v7_invoke_event_data *) pe.data;
_sj_invoke_cb(v7, ied->func, ied->this_obj, ied->args);
v7_disown(v7, &ied->args);
v7_disown(v7, &ied->this_obj);
v7_disown(v7, &ied->func);
free(ied);
break;
}
}
}
}
/* Int vector table, defined in startup_gcc.c */
extern void (*const g_pfnVectors[])(void);
void device_reboot(void) {
sj_system_restart(0);
}
/*!
\brief open spi communication port to be used for communicating with a SimpleLink device
Given an interface name and option flags, this function opens the spi communication port
and creates a file descriptor. This file descriptor can be used afterwards to read and
write data from and to this specific spi channel.
The SPI speed, clock polarity, clock phase, chip select and all other attributes are all
set to hardcoded values in this function.
\param ifName - points to the interface name/path. The interface name is an
optional attributes that the simple link driver receives
on opening the device. in systems that the spi channel is
not implemented as part of the os device drivers, this
parameter could be NULL.
\param flags - option flags
\return upon successful completion, the function shall open the spi channel and return
a non-negative integer representing the file descriptor.
Otherwise, -1 shall be returned
\sa spi_Close , spi_Read , spi_Write
\note
\warning
*/
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
SPICSDisable(ulBase);
//Disable SPI Channel
SPIDisable(ulBase);
// Reset SPI
SPIReset(ulBase);
//
// Configure SPI interface
//
SPIConfigSetExpClk(ulBase,PRCMPeripheralClockGet(PRCM_LSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
//g_ucDout[0]=0xFF;
//Simplelink_UDMAInit();
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
SPIFIFOEnable(ulBase,SPI_RX_FIFO);
SPIFIFOEnable(ulBase,SPI_TX_FIFO);
SPIDmaEnable(ulBase,SPI_RX_DMA);
SPIDmaEnable(ulBase,SPI_TX_DMA);
SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
IntEnable(INT_LSPI);
SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}
static void uart_int() {
int c = UARTCharGet(CONSOLE_UART);
struct prompt_event pe = {.type = PROMPT_CHAR_EVENT, .data = (void *) c};
osi_MsgQWrite(&s_v7_q, &pe, OSI_NO_WAIT);
MAP_UARTIntClear(CONSOLE_UART, UART_INT_RX);
}
void sj_prompt_init_hal(struct v7 *v7) {
(void) v7;
}
static void v7_task(void *arg) {
struct v7 *v7 = s_v7;
printf("\n\nSmart.JS for CC3200\n");
osi_MsgQCreate(&s_v7_q, "V7", sizeof(struct prompt_event), 32 /* len */);
osi_InterruptRegister(CONSOLE_UART_INT, uart_int, INT_PRIORITY_LVL_1);
MAP_UARTIntEnable(CONSOLE_UART, UART_INT_RX);
sl_Start(NULL, NULL, NULL);
v7 = s_v7 = init_v7(&v7);
sj_init_timers(v7);
sj_init_v7_ext(v7);
init_wifi(v7);
if (init_fs(v7) != 0) {
fprintf(stderr, "FS initialization failed.\n");
}
mongoose_init();
sj_init_http(v7);
init_i2cjs(v7);
/* Common config infrastructure. Mongoose & v7 must be initialized. */
init_device(v7);
v7_val_t res;
if (v7_exec_file(v7, "sys_init.js", &res) != V7_OK) {
fprintf(stderr, "Error: ");
v7_fprint(stderr, v7, res);
}
sj_prompt_init(v7);
while (1) {
struct prompt_event pe;
mongoose_poll(MONGOOSE_POLL_LENGTH_MS);
if (osi_MsgQRead(&s_v7_q, &pe, V7_POLL_LENGTH_MS) != OSI_OK) continue;
switch (pe.type) {
case PROMPT_CHAR_EVENT: {
sj_prompt_process_char((char) ((int) pe.data));
break;
}
case V7_INVOKE_EVENT: {
struct v7_invoke_event_data *ied =
(struct v7_invoke_event_data *) pe.data;
_sj_invoke_cb(v7, ied->func, ied->this_obj, ied->args);
v7_disown(v7, &ied->args);
v7_disown(v7, &ied->this_obj);
v7_disown(v7, &ied->func);
free(ied);
break;
}
}
}
}
/* Int vector table, defined in startup_gcc.c */
extern void (*const g_pfnVectors[])(void);
void device_reboot(void) {
sj_system_restart();
}
int main() {
MAP_IntVTableBaseSet((unsigned long) &g_pfnVectors[0]);
MAP_IntEnable(FAULT_SYSTICK);
MAP_IntMasterEnable();
PRCMCC3200MCUInit();
cc3200_leds_init();
/* Console UART init. */
MAP_PRCMPeripheralClkEnable(CONSOLE_UART_PERIPH, PRCM_RUN_MODE_CLK);
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* PIN_55 -> UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* PIN_57 -> UART0_RX */
MAP_UARTConfigSetExpClk(
CONSOLE_UART, MAP_PRCMPeripheralClockGet(CONSOLE_UART_PERIPH),
CONSOLE_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
MAP_UARTFIFODisable(CONSOLE_UART);
setvbuf(stdout, NULL, _IONBF, 0);
setvbuf(stderr, NULL, _IONBF, 0);
VStartSimpleLinkSpawnTask(8);
osi_TaskCreate(v7_task, (const signed char *) "v7", V7_STACK_SIZE + 256, NULL,
3, NULL);
osi_TaskCreate(blinkenlights_task, (const signed char *) "blink", 256, NULL,
9, NULL);
osi_start();
return 0;
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
unsigned long ulSpiBitRate;
tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR);
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
MAP_SPICSDisable(ulBase);
//Disable SPI Channel
MAP_SPIDisable(ulBase);
// Reset SPI
MAP_SPIReset(ulBase);
//
// Configure SPI interface
//
if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 )
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32)
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33)
{
ulSpiBitRate = SPI_RATE_20M;
}
MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI),
ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO);
MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO);
MAP_SPIDmaEnable(ulBase,SPI_RX_DMA);
MAP_SPIDmaEnable(ulBase,SPI_TX_DMA);
MAP_SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
MAP_IntEnable(INT_LSPI);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
MAP_SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}
void sj_prompt_init_hal(struct v7 *v7) {
(void) v7;
osi_InterruptRegister(CONSOLE_UART_INT, uart_int, INT_PRIORITY_LVL_1);
MAP_UARTIntEnable(CONSOLE_UART, UART_INT_RX | UART_INT_RT);
}
