// output a displacement
static void outdispl(void) {
if ( is_displ_indx() ) {
out_symbol('(');
outaddr(cmd.Op1, false);
out_symbol(',');
if ( !(ash.uflag & UAS_INDX_NOSPACE)) OutChar(' ' );
outreg(cmd.Op1.reg);
out_symbol(')');
return;
}
if ( is_displ_indy() ) {
out_symbol('(');
outaddr(cmd.Op1, false);
out_symbol(')');
out_symbol(',');
OutChar(' ');
outreg(cmd.Op1.reg);
return;
}
if ( is_displ_zpx() || is_displ_zpy() || is_displ_absx() || is_displ_absy() ) {
outaddr(cmd.Op1, false);
out_symbol(',');
OutChar(' ');
outreg(cmd.Op1.reg);
return;
}
INTERR(10023);
}
/**
* @ingroup lte_ratematching
*
* Main DSP function
*
*/
int work(void **inp, void **out) {
int i, in_pkt_len, out_pkt_len, j;
int rcv_samples;
char *input, *output;
param_get_int(pre_padding_id, &pre_padding);
param_get_int(post_padding_id, &post_padding);
param_get_int(nof_packets_id, &nof_packets);
for (i=0;i<NOF_INPUT_ITF;i++) {
input = inp[i];
output = out[i];
rcv_samples = get_input_samples(i);
moddebug("%d samples received on input interface %d.\n",rcv_samples,i);
if (rcv_samples == 0) {
moddebug("%d samples to process. Returning.\n", rcv_samples);
continue;
}
if ((rcv_samples) % nof_packets) {
moderror_msg("Received samples (%d) should multiple of "
"nof_packets (%d)\n", rcv_samples, nof_packets);
return -1;
}
in_pkt_len = rcv_samples / nof_packets;
if (direction) {
out_pkt_len = in_pkt_len - pre_padding - post_padding;
} else {
out_pkt_len = in_pkt_len + pre_padding + post_padding;
}
if (in_pkt_len) {
if (direction) {
for (j=0;j<nof_packets;j++) {
memcpy(outaddr(0),inaddr(pre_padding),input_sample_sz*out_pkt_len);
}
} else {
for (j=0;j<nof_packets;j++) {
memset(outaddr(0),0,input_sample_sz*pre_padding);
memcpy(outaddr(pre_padding),inaddr(0),input_sample_sz*in_pkt_len);
memset(outaddr(pre_padding+in_pkt_len),0,input_sample_sz*post_padding);
}
}
moddebug("%d samples sent to output interface %d.\n",out_pkt_len*nof_packets, i);
set_output_samples(i,out_pkt_len*nof_packets);
}
}
return 0;
}
// output an operand
bool idaapi outop(op_t &op) {
switch ( op.type ) {
// register
case o_reg:
outreg(op.reg);
break;
// immediate
case o_imm:
if ( (op.specflag1 & OP_IMM_BIT) == 0 )
out_symbol('#');
OutValue(op, OOFW_IMM);
break;
// data / code memory address
case o_near:
case o_mem:
outaddr(op);
break;
// displ
case o_displ:
outdispl();
break;
// ignore void operands
case o_void:
break;
default:
INTERR(10024);
}
return 1;
}
