u32 read_pci_config_word(u8 bus, u8 slot,u8 func,u8 offset)
{
u32 address;
u32 lbus = (u32)bus;
u32 lslot = (u32)slot;
u32 lfunc = (u32)func;
address = (u32)((lbus << 16) | (lslot << 11) |
(lfunc << 8) | (offset & 0xfc) | ((u32)0x80000000));
outdw(address,0xCF8);
return indw(0xCFC);
}
/*!
* \brief Initialize system timer.
*
* This function is automatically called by Nut/OS
* during system initialization.
*
* Nut/OS uses on-chip timer 0 for its timer services.
* Applications should not modify any registers of this
* timer, but make use of the Nut/OS timer API. Timer 1
* and timer 2 are available to applications.
*/
void NutRegisterTimer(void (*handler) (void *))
{
os_handler = handler;
/* Disable master interrupt. */
outw(REG_IME, 0);
/* Set global interrupt vector. */
NutRegisterIrqHandler(&sig_TMR3, Timer3Entry, 0);
/* Enable timer and timer interrupts. */
outdw(REG_TMR3CNT, TMR_IRQ_ENA | TMR_ENA | 48756);
/* Enable timer 3 interrupts. */
outw(REG_IE, inw(REG_IE) | INT_TMR3);
/* Enable master interrupt. */
outw(REG_IME, 1);
}
/*!
* \brief Initialize system timer.
*
* This function is automatically called by Nut/OS
* during system initialization.
*
* Nut/OS uses on-chip timer 0 for its timer services.
* Applications should not modify any registers of this
* timer, but make use of the Nut/OS timer API. Timer 1
* and timer 2 are available to applications.
*/
void NutRegisterTimer(void (*handler) (void *))
{
os_handler = handler;
#if defined(MCU_AT91R40008)
/* Disable the Clock Counter */
outr(TC0_CCR, TC_CLKDIS);
/* Disable all interrupts */
outr(TC0_IDR, 0xFFFFFFFF);
/* Clear the status register. */
dummy = inr(TC0_SR);
/* Select divider and compare trigger */
outr(TC0_CMR, TC_CLKS_MCK32 | TC_CPCTRG);
/* Enable the Clock counter */
outr(TC0_CCR, TC_CLKEN);
/* Validate the RC compare interrupt */
outr(TC0_IER, TC_CPCS);
/* Disable timer 0 interrupts. */
outr(AIC_IDCR, _BV(TC0_ID));
/* Set the TC0 IRQ handler address */
outr(AIC_SVR(4), (unsigned int)Timer0Entry);
/* Set the trigg and priority for timer 0 interrupt */
/* Level 7 is highest, level 0 lowest. */
outr(AIC_SMR(4), (AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4));
/* Clear timer 0 interrupt */
outr(AIC_ICCR, _BV(TC0_ID));
/* Enable timer 0 interrupts */
outr(AIC_IECR, _BV(TC0_ID));
/* Set compare value for 1 ms. */
outr(TC0_RC, 0x80F);
/* Software trigger starts the clock. */
outr(TC0_CCR, TC_SWTRG);
#elif defined(MCU_S3C4510B)
INT_DISABLE(IRQ_TIMER);
CSR_WRITE(TCNT0, 0);
CSR_WRITE(TDATA0, CLOCK_TICK_RATE);
CSR_WRITE(TMOD, TMOD_TIMER0_VAL);
CLEAR_PEND_INT(IRQ_TIMER);
NutRegisterIrqHandler(
&InterruptHandlers[IRQ_TIMER], handler, 0);
INT_ENABLE(IRQ_TIMER);
#elif defined(MCU_GBA)
/* Disable master interrupt. */
outw(REG_IME, 0);
/* Set global interrupt vector. */
NutRegisterIrqHandler(&sig_TMR3, Timer3Entry, 0);
/* Enable timer and timer interrupts. */
outdw(REG_TMR3CNT, TMR_IRQ_ENA | TMR_ENA | 48756);
/* Enable timer 3 interrupts. */
outw(REG_IE, inw(REG_IE) | INT_TMR3);
/* Enable master interrupt. */
outw(REG_IME, 1);
#else
#warning "MCU not defined"
#endif
}