void cos_shutdown_memory(void) { int i; for (i = 0 ; i < COS_MAX_MEMORY ; i++) { paddr_t addr = cos_pages[i].addr; if (0 != addr) { cos_free_page(pa_to_va((void*)addr)); addr = 0; } } }
#include "x86.h" #include "headers/tty.h" #include "vm.h" #include "irq.h" #include "headers/time.h" #include "debug.h" #include "string.h" #include "headers/term.h" #include "kernel.h" Console ttys[NR_TTY]; Console *current_consl; const char *ttynames[NR_TTY] = {"tty1", "tty2", "tty3", "tty4"}; static uint16_t *vmem = (void*)pa_to_va(0xb8000); static uint16_t vbuf[NR_TTY][SCR_W * SCR_H * 2]; char banner[SCR_W + 1]; static uint16_t draw(char ch) { return (C_BLACK << 12) | (C_WHITE << 8) | ch; } static void scrup(Console *c) { int i; if (c->scr + c->wh >= c->vbuf + c->size) { for (i = c->w; i < c->size; i ++) c->vbuf[i - c->w] = c->vbuf[i];
void *request_io_mem(unsigned long addr) { return (void *)pa_to_va(addr); }
void apic_init (struct cpu * core) { struct apic_dev * apic = NULL; ulong_t base_addr; uint32_t val; apic = (struct apic_dev*)malloc(sizeof(struct apic_dev)); if (!apic) { panic("Could not allocate apic struct\n"); } memset(apic, 0, sizeof(struct apic_dev)); core->apic = apic; if (!check_apic_avail()) { panic("No APIC found on core %u, dying\n", core->id); } /* In response to AMD erratum #663 * the damn thing may give us lint interrupts * even when we have them masked */ if (nk_is_amd() && cpuid_get_family() == 0x15) { APIC_DEBUG("Writing Bridge Ctrl MSR for AMD Errata #663\n"); msr_write(AMD_MSR_NBRIDGE_CTL, msr_read(AMD_MSR_NBRIDGE_CTL) | (1ULL<<23) | (1ULL<<54)); } base_addr = apic_get_base_addr(); /* idempotent when not compiled as HRT */ apic->base_addr = pa_to_va(base_addr); #ifndef NAUT_CONFIG_HVM_HRT if (core->is_bsp) { /* map in the lapic as uncacheable */ if (nk_map_page_nocache(apic->base_addr, PTE_PRESENT_BIT|PTE_WRITABLE_BIT, PS_4K) == -1) { panic("Could not map APIC\n"); } } #endif apic->version = apic_get_version(apic); apic->id = apic_get_id(apic); #ifndef NAUT_CONFIG_XEON_PHI if (apic->version < 0x10 || apic->version > 0x15) { panic("Unsupported APIC version (0x%1x)\n", (unsigned)apic->version); } #endif val = apic_read(apic, APIC_REG_LDR) & ~APIC_LDR_MASK; val |= SET_APIC_LOGICAL_ID(0); apic_write(apic, APIC_REG_LDR, val); apic_write(apic, APIC_REG_TPR, apic_read(apic, APIC_REG_TPR) & 0xffffff00); // accept all interrupts apic_write(apic, APIC_REG_LVTT, APIC_DEL_MODE_FIXED | APIC_LVT_DISABLED); // disable timer interrupts intially apic_write(apic, APIC_REG_LVTPC, APIC_DEL_MODE_FIXED | APIC_LVT_DISABLED | APIC_PC_INT_VEC); // disable perf cntr interrupts apic_write(apic, APIC_REG_LVTTHMR, APIC_DEL_MODE_FIXED | APIC_LVT_DISABLED | APIC_THRML_INT_VEC); // disable thermal interrupts /* do we have AMD extended LVT entries to deal with */ if (nk_is_amd() && amd_has_ext_lvt(apic)) { amd_setup_ext_lvt(apic); } /* mask 8259a interrupts */ apic_write(apic, APIC_REG_LVT0, APIC_DEL_MODE_EXTINT | APIC_LVT_DISABLED); /* only BSP takes NMI interrupts */ apic_write(apic, APIC_REG_LVT1, APIC_DEL_MODE_NMI | (core->is_bsp ? 0 : APIC_LVT_DISABLED)); apic_write(apic, APIC_REG_LVTERR, APIC_DEL_MODE_FIXED | APIC_ERROR_INT_VEC); // allow error interrupts // clear the ESR apic_write(apic, APIC_REG_ESR, 0u); apic_global_enable(); // assign interrupt handlers if (core->is_bsp) { if (register_int_handler(APIC_NULL_KICK_VEC, null_kick, apic) != 0) { panic("Could not register null kick interrupt handler\n"); } if (register_int_handler(APIC_SPUR_INT_VEC, spur_int_handler, apic) != 0) { panic("Could not register spurious interrupt handler\n"); } if (register_int_handler(APIC_ERROR_INT_VEC, error_int_handler, apic) != 0) { panic("Could not register spurious interrupt handler\n"); return; } /* we shouldn't ever get these, but just in case */ if (register_int_handler(APIC_PC_INT_VEC, pc_int_handler, apic) != 0) { panic("Could not register perf counter interrupt handler\n"); return; } if (register_int_handler(APIC_THRML_INT_VEC, thermal_int_handler, apic) != 0) { panic("Could not register thermal interrupt handler\n"); return; } if (register_int_handler(APIC_EXT_LVT_DUMMY_VEC, dummy_int_handler, apic) != 0) { panic("Could not register dummy ext lvt handler\n"); return; } } apic_assign_spiv(apic, APIC_SPUR_INT_VEC); /* turn it on */ apic_sw_enable(apic); /* pass in quantum as milliseconds */ #ifndef NAUT_CONFIG_XEON_PHI apic_timer_setup(apic, 1000/NAUT_CONFIG_HZ); #endif apic_dump(apic); }
//#define ENTRY 0X8048074 PCB* create_process(uint8_t *buf) { struct ELFHeader *elf = (struct ELFHeader*) buf; struct ProgramHeader *ph, *eph; uint32_t va, eva, pa, len, sublen, tmpva, offset; uint8_t *kst; int ret; PCB* pcb = create_kthread((void*)NULL); ph = (struct ProgramHeader*)((char*)elf + elf->phoff); eph = ph + elf->phnum; assert(pcb != NULL); printk("in create process pid=%d\n",pcb->pid); for(; ph < eph; ph++) { if(ph->type != PT_LOAD) continue; va = ph->vaddr; //in boot/main.c is paddr, it may be a bug len = ph->memsz; eva = va + len; printk("segment start = %x\n",va); printk("segment end = %x\n",eva); //request new page here //start= ph->vaddr, len=ph->memsz // printk("before alloc pages...va=%x\n",va); ret = alloc_pages(pcb,va,len); printk("after alloc pages\n"); assert(ret == 0); // must be successful printk("after alloc pages and assertion\n"); //attention: virtual adrress to physical address offset = ph->off; for(; va < eva;) { pa = pcb_va_to_pa(pcb,va); printk("physical address = %x\n",pa); kst = (uint8_t*)pa_to_va(pa); //virtual address printk("virtual address = %x\n",kst); tmpva = va; va = to_next_page(va) < eva ? to_next_page(va) : eva; //when va == ea this loop end sublen = va - tmpva; memcpy(kst, (char*)elf + offset,sublen); offset += sublen; } } printk("before alloc stack\n"); ret = alloc_user_stack(pcb); assert(ret==0); printk("after alloc user stack\n"); struct TrapFrame* tf = ((struct TrapFrame*)(pcb->tf)); tf->eip = elf->entry;//ENTRY; //set user stack here tf->cs = SELECTOR_USER(SEG_USER_CODE); tf->ds = SELECTOR_USER(SEG_USER_DATA); tf->irq = 1000; tf->ss = SELECTOR_USER(SEG_USER_DATA); tf->esp = USER_STACK_END; //should I set tf->ebp? return pcb; }