/* Basic test of the panel uclass */ static int dm_test_panel(struct unit_test_state *uts) { struct udevice *dev, *pwm, *gpio, *reg; uint period_ns; uint duty_ns; bool enable; bool polarity; ut_assertok(uclass_first_device_err(UCLASS_PANEL, &dev)); ut_assertok(uclass_first_device_err(UCLASS_PWM, &pwm)); ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio)); ut_assertok(regulator_get_by_platname("VDD_EMMC_1.8V", ®)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, &enable, &polarity)); ut_asserteq(false, enable); ut_asserteq(false, regulator_get_enable(reg)); ut_assertok(panel_enable_backlight(dev)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, &enable, &polarity)); ut_asserteq(1000, period_ns); ut_asserteq(170 * 1000 / 256, duty_ns); ut_asserteq(true, enable); ut_asserteq(false, polarity); ut_asserteq(1, sandbox_gpio_get_value(gpio, 1)); ut_asserteq(true, regulator_get_enable(reg)); ut_assertok(panel_set_backlight(dev, 40)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, &enable, &polarity)); ut_asserteq(64 * 1000 / 256, duty_ns); ut_assertok(panel_set_backlight(dev, BACKLIGHT_MAX)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, &enable, &polarity)); ut_asserteq(255 * 1000 / 256, duty_ns); ut_assertok(panel_set_backlight(dev, BACKLIGHT_MIN)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, &enable, &polarity)); ut_asserteq(0 * 1000 / 256, duty_ns); ut_asserteq(1, sandbox_gpio_get_value(gpio, 1)); ut_assertok(panel_set_backlight(dev, BACKLIGHT_DEFAULT)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, &enable, &polarity)); ut_asserteq(true, enable); ut_asserteq(170 * 1000 / 256, duty_ns); ut_assertok(panel_set_backlight(dev, BACKLIGHT_OFF)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, &enable, &polarity)); ut_asserteq(0 * 1000 / 256, duty_ns); ut_asserteq(0, sandbox_gpio_get_value(gpio, 1)); ut_asserteq(false, regulator_get_enable(reg)); return 0; }
static int tegra_sor_set_backlight(struct udevice *dev, int percent) { struct tegra_dc_sor_data *priv = dev_get_priv(dev); int ret; ret = panel_enable_backlight(priv->panel); if (ret) { debug("sor: Cannot enable panel backlight\n"); return ret; } return 0; }
int rk_lvds_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { struct rk_lvds_priv *priv = dev_get_priv(dev); struct display_plat *uc_plat = dev_get_uclass_platdata(dev); int ret = 0; unsigned int val = 0; ret = panel_enable_backlight(priv->panel); if (ret) { debug("%s: backlight error: %d\n", __func__, ret); return ret; } /* Select the video source */ if (uc_plat->source_id) val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT | (RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16); else val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16; rk_setreg(&priv->grf->soc_con6, val); /* Select data transfer format */ val = priv->format; if (priv->output == LVDS_OUTPUT_DUAL) val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN; else if (priv->output == LVDS_OUTPUT_SINGLE) val |= LVDS_CH0_EN; else if (priv->output == LVDS_OUTPUT_RGB) val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN; val |= (0xffff << 16); rk_setreg(&priv->grf->soc_con7, val); /* Enable LVDS PHY */ if (priv->output == LVDS_OUTPUT_RGB) { lvds_writel(priv, RK3288_LVDS_CH0_REG0, RK3288_LVDS_CH0_REG0_TTL_EN | RK3288_LVDS_CH0_REG0_LANECK_EN | RK3288_LVDS_CH0_REG0_LANE4_EN | RK3288_LVDS_CH0_REG0_LANE3_EN | RK3288_LVDS_CH0_REG0_LANE2_EN | RK3288_LVDS_CH0_REG0_LANE1_EN | RK3288_LVDS_CH0_REG0_LANE0_EN); lvds_writel(priv, RK3288_LVDS_CH0_REG2, RK3288_LVDS_PLL_FBDIV_REG2(0x46)); lvds_writel(priv, RK3288_LVDS_CH0_REG3, RK3288_LVDS_PLL_FBDIV_REG3(0x46)); lvds_writel(priv, RK3288_LVDS_CH0_REG4, RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE | RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE | RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE | RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE | RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE | RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE); lvds_writel(priv, RK3288_LVDS_CH0_REG5, RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA | RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA | RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA | RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA | RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA | RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA); lvds_writel(priv, RK3288_LVDS_CH0_REGD, RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); lvds_writel(priv, RK3288_LVDS_CH0_REG20, RK3288_LVDS_CH0_REG20_LSB); } else { lvds_writel(priv, RK3288_LVDS_CH0_REG0, RK3288_LVDS_CH0_REG0_LVDS_EN | RK3288_LVDS_CH0_REG0_LANECK_EN | RK3288_LVDS_CH0_REG0_LANE4_EN | RK3288_LVDS_CH0_REG0_LANE3_EN | RK3288_LVDS_CH0_REG0_LANE2_EN | RK3288_LVDS_CH0_REG0_LANE1_EN | RK3288_LVDS_CH0_REG0_LANE0_EN); lvds_writel(priv, RK3288_LVDS_CH0_REG1, RK3288_LVDS_CH0_REG1_LANECK_BIAS | RK3288_LVDS_CH0_REG1_LANE4_BIAS | RK3288_LVDS_CH0_REG1_LANE3_BIAS | RK3288_LVDS_CH0_REG1_LANE2_BIAS | RK3288_LVDS_CH0_REG1_LANE1_BIAS | RK3288_LVDS_CH0_REG1_LANE0_BIAS); lvds_writel(priv, RK3288_LVDS_CH0_REG2, RK3288_LVDS_CH0_REG2_RESERVE_ON | RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE | RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE | RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE | RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE | RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE | RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE | RK3288_LVDS_PLL_FBDIV_REG2(0x46)); lvds_writel(priv, RK3288_LVDS_CH0_REG3, RK3288_LVDS_PLL_FBDIV_REG3(0x46)); lvds_writel(priv, RK3288_LVDS_CH0_REG4, 0x00); lvds_writel(priv, RK3288_LVDS_CH0_REG5, 0x00); lvds_writel(priv, RK3288_LVDS_CH0_REGD, RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); lvds_writel(priv, RK3288_LVDS_CH0_REG20, RK3288_LVDS_CH0_REG20_LSB); } /* Power on */ writel(RK3288_LVDS_CFG_REGC_PLL_ENABLE, priv->regs + RK3288_LVDS_CFG_REGC); writel(RK3288_LVDS_CFG_REG21_TX_ENABLE, priv->regs + RK3288_LVDS_CFG_REG21); return 0; }