static int __init mpc832x_spi_init(void) { par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */ par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */ par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */ par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */ par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */ par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */ par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */ return fsl_spi_init(&mpc832x_spi_boardinfo, 1, mpc83xx_spi_activate_cs, mpc83xx_spi_deactivate_cs); }
int par_io_of_config(struct device_node *np) { struct device_node *pio; const phandle *ph; int pio_map_len; const unsigned int *pio_map; if (par_io == NULL) { printk(KERN_ERR "par_io not initialized\n"); return -1; } ph = of_get_property(np, "pio-handle", NULL); if (ph == NULL) { printk(KERN_ERR "pio-handle not available\n"); return -1; } pio = of_find_node_by_phandle(*ph); pio_map = of_get_property(pio, "pio-map", &pio_map_len); if (pio_map == NULL) { printk(KERN_ERR "pio-map is not set!\n"); return -1; } pio_map_len /= sizeof(unsigned int); if ((pio_map_len % 6) != 0) { printk(KERN_ERR "pio-map format wrong!\n"); return -1; } while (pio_map_len > 0) { par_io_config_pin((u8) pio_map[0], (u8) pio_map[1], (int) pio_map[2], (int) pio_map[3], (int) pio_map[4], (int) pio_map[5]); pio_map += 6; pio_map_len -= 6; } of_node_put(pio); return 0; }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); #ifdef CONFIG_QE_USB /* Must fixup Par IO before QE GPIO chips are registered. */ par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */ par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */ par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */ par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */ par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */ par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */ par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */ #endif /* CONFIG_QE_USB */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ uint svid; /* Reset the Ethernet PHY */ #define BCSR9_GETHRST 0x20 clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); setbits8(&bcsr_regs[9], BCSR9_GETHRST); /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ svid = mfspr(SPRN_SVR); if (svid == 0x80480021) { void __iomem *immap; immap = ioremap(get_immrbase() + 0x14a8, 8); /* * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ setbits32(immap, 0x0c003000); /* * IMMR + 0x14AC[20:27] = 10101010 * (data delay for both UCC's) */ clrsetbits_be32(immap + 4, 0xff0, 0xaa0); iounmap(immap); } iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
/* ************************************************************************ * * Setup the architecture * */ static void __init twr_p1025_setup_arch(void) { #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("twr_p1025_setup_arch()", 0); mpc85xx_smp_init(); fsl_pci_assign_primary(); #ifdef CONFIG_QUICC_ENGINE np = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!np) { np = of_find_node_by_name(NULL, "qe"); if (!np) { printk(KERN_ERR "Could not find Quicc Engine node\n"); goto qe_fail; } } qe_reset(); of_node_put(np); np = of_find_node_by_name(NULL, "par_io"); if (np) { struct device_node *ucc; par_io_init(np); of_node_put(np); for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); } #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) if (machine_is(twr_p1025)) { struct ccsr_guts __iomem *guts; np = of_find_node_by_name(NULL, "global-utilities"); if (np) { guts = of_iomap(np, 0); if (!guts) pr_err("twr_p1025: could not map global utilities register\n"); else { /* P1025 has pins muxed for QE and other functions. To * enable QE UEC mode, we need to set bit QE0 for UCC1 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 * and QE12 for QE MII management signals in PMUXCR * register. */ printk(KERN_INFO "P1025 pinmux configured for QE\n"); /* Set QE mux bits in PMUXCR */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); iounmap(guts); #if defined(CONFIG_SERIAL_QE) || defined(CONFIG_SERIAL_QE_MODULE) /* On P1025TWR board, the UCC7 acted as UART port. * However, The UCC7's CTS pin is low level in default, * it will impact the transmission in full duplex * communication. So disable the Flow control pin PA18. * The UCC7 UART just can use RXD and TXD pins. */ par_io_config_pin(0, 18, 0, 0, 0, 0); #endif /* Drive PB29 to CPLD low - CPLD will then change * muxing from LBC to QE */ par_io_config_pin(1, 29, 1, 0, 0, 0); par_io_data_set(1, 29, 0); } of_node_put(np); } } #endif qe_fail: #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "TWR-P1025 board from Freescale Semiconductor\n"); }
static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); #ifdef CONFIG_QE_USB /* */ par_io_config_pin(1, 2, 1, 0, 3, 0); /* */ par_io_config_pin(1, 3, 1, 0, 3, 0); /* */ par_io_config_pin(1, 8, 1, 0, 1, 0); /* */ par_io_config_pin(1, 10, 2, 0, 3, 0); /* */ par_io_config_pin(1, 9, 2, 1, 3, 0); /* */ par_io_config_pin(1, 11, 2, 1, 3, 0); /* */ par_io_config_pin(2, 20, 2, 0, 1, 0); /* */ #endif /* */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ uint svid; /* */ #define BCSR9_GETHRST 0x20 clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); setbits8(&bcsr_regs[9], BCSR9_GETHRST); /* */ svid = mfspr(SPRN_SVR); if (svid == 0x80480021) { void __iomem *immap; immap = ioremap(get_immrbase() + 0x14a8, 8); /* */ setbits32(immap, 0x0c003000); /* */ clrsetbits_be32(immap + 4, 0xff0, 0xaa0); iounmap(immap); } iounmap(bcsr_regs); of_node_put(np); } #endif /* */ }