static void partner_bank_switch(running_machine &machine) { partner_state *state = machine.driver_data<partner_state>(); address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM); UINT8 *rom = state->memregion("maincpu")->base(); UINT8 *ram = machine.device<ram_device>(RAM_TAG)->pointer(); space.install_write_bank(0x0000, 0x07ff, "bank1"); space.install_write_bank(0x0800, 0x3fff, "bank2"); space.install_write_bank(0x4000, 0x5fff, "bank3"); space.install_write_bank(0x6000, 0x7fff, "bank4"); space.install_write_bank(0x8000, 0x9fff, "bank5"); space.install_write_bank(0xa000, 0xb7ff, "bank6"); space.install_write_bank(0xb800, 0xbfff, "bank7"); space.install_write_bank(0xc000, 0xc7ff, "bank8"); space.install_write_bank(0xc800, 0xcfff, "bank9"); space.install_write_bank(0xd000, 0xd7ff, "bank10"); space.unmap_write(0xdc00, 0xddff); space.install_read_bank (0xdc00, 0xddff, "bank11"); space.unmap_write(0xe000, 0xe7ff); space.unmap_write(0xe800, 0xffff); // BANK 1 (0x0000 - 0x07ff) if (state->m_mem_page==0) { space.unmap_write(0x0000, 0x07ff); state->membank("bank1")->set_base(rom + 0x10000); } else { if (state->m_mem_page==7) { state->membank("bank1")->set_base(ram + 0x8000); } else { state->membank("bank1")->set_base(ram + 0x0000); } } // BANK 2 (0x0800 - 0x3fff) if (state->m_mem_page==7) { state->membank("bank2")->set_base(ram + 0x8800); } else { state->membank("bank2")->set_base(ram + 0x0800); } // BANK 3 (0x4000 - 0x5fff) if (state->m_mem_page==7) { state->membank("bank3")->set_base(ram + 0xC000); } else { if (state->m_mem_page==10) { //window 1 space.unmap_write(0x4000, 0x5fff); partner_window_1(machine, 3, 0, rom); } else { state->membank("bank3")->set_base(ram + 0x4000); } } // BANK 4 (0x6000 - 0x7fff) if (state->m_mem_page==7) { state->membank("bank4")->set_base(ram + 0xe000); } else { state->membank("bank4")->set_base(ram + 0x6000); } // BANK 5 (0x8000 - 0x9fff) switch (state->m_mem_page) { case 5: case 10: //window 2 space.unmap_write(0x8000, 0x9fff); partner_window_2(machine, 5, 0, rom); break; case 8: case 9: //window 1 space.unmap_write(0x8000, 0x9fff); partner_window_1(machine, 5, 0, rom); break; case 7: state->membank("bank5")->set_base(ram + 0x0000); break; default: state->membank("bank5")->set_base(ram + 0x8000); break; } // BANK 6 (0xa000 - 0xb7ff) switch (state->m_mem_page) { case 5: case 10: //window 2 space.unmap_write(0xa000, 0xb7ff); partner_window_2(machine, 6, 0, rom); break; case 6: case 8: //BASIC space.unmap_write(0xa000, 0xb7ff); state->membank("bank6")->set_base(rom + 0x12000); // BASIC break; case 7: state->membank("bank6")->set_base(ram + 0x2000); break; default: state->membank("bank6")->set_base(ram + 0xa000); break; } // BANK 7 (0xb800 - 0xbfff) switch (state->m_mem_page) { case 4: case 5: case 10: //window 2 space.unmap_write(0xb800, 0xbfff); partner_window_2(machine, 7, 0x1800, rom); break; case 6: case 8: //BASIC space.unmap_write(0xb800, 0xbfff); state->membank("bank7")->set_base(rom + 0x13800); // BASIC break; case 7: state->membank("bank7")->set_base(ram + 0x3800); break; default: state->membank("bank7")->set_base(ram + 0xb800); break; } // BANK 8 (0xc000 - 0xc7ff) switch (state->m_mem_page) { case 7: state->membank("bank8")->set_base(ram + 0x4000); break; case 8: case 10: space.unmap_write(0xc000, 0xc7ff); state->membank("bank8")->set_base(rom + 0x10000); break; default: state->membank("bank8")->set_base(ram + 0xc000); break; } // BANK 9 (0xc800 - 0xcfff) switch (state->m_mem_page) { case 7: state->membank("bank9")->set_base(ram + 0x4800); break; case 8: case 9: // window 2 space.unmap_write(0xc800, 0xcfff); partner_window_2(machine, 9, 0, rom); break; case 10: space.unmap_write(0xc800, 0xcfff); state->membank("bank9")->set_base(rom + 0x10800); break; default: state->membank("bank9")->set_base(ram + 0xc800); break; } // BANK 10 (0xd000 - 0xd7ff) switch (state->m_mem_page) { case 7: state->membank("bank10")->set_base(ram + 0x5000); break; case 8: case 9: // window 2 space.unmap_write(0xd000, 0xd7ff); partner_window_2(machine, 10, 0x0800, rom); break; default: state->membank("bank10")->set_base(ram + 0xd000); break; } // BANK 11 (0xdc00 - 0xddff) partner_iomap_bank(machine,rom); // BANK 12 (0xe000 - 0xe7ff) if (state->m_mem_page==1) { state->membank("bank12")->set_base(rom + 0x10000); } else { //window 1 partner_window_1(machine, 12, 0, rom); } // BANK 13 (0xe800 - 0xffff) switch (state->m_mem_page) { case 3: case 4: case 5: // window 1 partner_window_1(machine, 13, 0x800, rom); break; default: // BIOS state->membank("bank13")->set_base(rom + 0x10800); break; } }
void partner_state::partner_bank_switch() { address_space &space = m_maincpu->space(AS_PROGRAM); UINT8 *rom = memregion("maincpu")->base(); UINT8 *ram = m_ram->pointer(); space.install_write_bank(0x0000, 0x07ff, "bank1"); space.install_write_bank(0x0800, 0x3fff, "bank2"); space.install_write_bank(0x4000, 0x5fff, "bank3"); space.install_write_bank(0x6000, 0x7fff, "bank4"); space.install_write_bank(0x8000, 0x9fff, "bank5"); space.install_write_bank(0xa000, 0xb7ff, "bank6"); space.install_write_bank(0xb800, 0xbfff, "bank7"); space.install_write_bank(0xc000, 0xc7ff, "bank8"); space.install_write_bank(0xc800, 0xcfff, "bank9"); space.install_write_bank(0xd000, 0xd7ff, "bank10"); space.unmap_write(0xdc00, 0xddff); space.install_read_bank (0xdc00, 0xddff, "bank11"); space.unmap_write(0xe000, 0xe7ff); space.unmap_write(0xe800, 0xffff); // BANK 1 (0x0000 - 0x07ff) if (m_mem_page==0) { space.unmap_write(0x0000, 0x07ff); membank("bank1")->set_base(rom + 0x10000); } else { if (m_mem_page==7) { membank("bank1")->set_base(ram + 0x8000); } else { membank("bank1")->set_base(ram + 0x0000); } } // BANK 2 (0x0800 - 0x3fff) if (m_mem_page==7) { membank("bank2")->set_base(ram + 0x8800); } else { membank("bank2")->set_base(ram + 0x0800); } // BANK 3 (0x4000 - 0x5fff) if (m_mem_page==7) { membank("bank3")->set_base(ram + 0xC000); } else { if (m_mem_page==10) { //window 1 space.unmap_write(0x4000, 0x5fff); partner_window_1(3, 0, rom); } else { membank("bank3")->set_base(ram + 0x4000); } } // BANK 4 (0x6000 - 0x7fff) if (m_mem_page==7) { membank("bank4")->set_base(ram + 0xe000); } else { membank("bank4")->set_base(ram + 0x6000); } // BANK 5 (0x8000 - 0x9fff) switch (m_mem_page) { case 5: case 10: //window 2 space.unmap_write(0x8000, 0x9fff); partner_window_2(5, 0, rom); break; case 8: case 9: //window 1 space.unmap_write(0x8000, 0x9fff); partner_window_1(5, 0, rom); break; case 7: membank("bank5")->set_base(ram + 0x0000); break; default: membank("bank5")->set_base(ram + 0x8000); break; } // BANK 6 (0xa000 - 0xb7ff) switch (m_mem_page) { case 5: case 10: //window 2 space.unmap_write(0xa000, 0xb7ff); partner_window_2(6, 0, rom); break; case 6: case 8: //BASIC space.unmap_write(0xa000, 0xb7ff); membank("bank6")->set_base(rom + 0x12000); // BASIC break; case 7: membank("bank6")->set_base(ram + 0x2000); break; default: membank("bank6")->set_base(ram + 0xa000); break; } // BANK 7 (0xb800 - 0xbfff) switch (m_mem_page) { case 4: case 5: case 10: //window 2 space.unmap_write(0xb800, 0xbfff); partner_window_2(7, 0x1800, rom); break; case 6: case 8: //BASIC space.unmap_write(0xb800, 0xbfff); membank("bank7")->set_base(rom + 0x13800); // BASIC break; case 7: membank("bank7")->set_base(ram + 0x3800); break; default: membank("bank7")->set_base(ram + 0xb800); break; } // BANK 8 (0xc000 - 0xc7ff) switch (m_mem_page) { case 7: membank("bank8")->set_base(ram + 0x4000); break; case 8: case 10: space.unmap_write(0xc000, 0xc7ff); membank("bank8")->set_base(rom + 0x10000); break; default: membank("bank8")->set_base(ram + 0xc000); break; } // BANK 9 (0xc800 - 0xcfff) switch (m_mem_page) { case 7: membank("bank9")->set_base(ram + 0x4800); break; case 8: case 9: // window 2 space.unmap_write(0xc800, 0xcfff); partner_window_2(9, 0, rom); break; case 10: space.unmap_write(0xc800, 0xcfff); membank("bank9")->set_base(rom + 0x10800); break; default: membank("bank9")->set_base(ram + 0xc800); break; } // BANK 10 (0xd000 - 0xd7ff) switch (m_mem_page) { case 7: membank("bank10")->set_base(ram + 0x5000); break; case 8: case 9: // window 2 space.unmap_write(0xd000, 0xd7ff); partner_window_2(10, 0x0800, rom); break; default: membank("bank10")->set_base(ram + 0xd000); break; } // BANK 11 (0xdc00 - 0xddff) partner_iomap_bank(rom); // BANK 12 (0xe000 - 0xe7ff) if (m_mem_page==1) { membank("bank12")->set_base(rom + 0x10000); } else { //window 1 partner_window_1(12, 0, rom); } // BANK 13 (0xe800 - 0xffff) switch (m_mem_page) { case 3: case 4: case 5: // window 1 partner_window_1(13, 0x800, rom); break; default: // BIOS membank("bank13")->set_base(rom + 0x10800); break; } }