/* * Initialization. Try all known PCI access methods. Note that we support * using both PCI BIOS and direct access: in such cases, we use I/O ports * to access config space, but we still keep BIOS order of cards to be * compatible with 2.0.X. This should go away some day. */ static int __init pcibios_init(void) { ioport_resource.start = 0xA0000000; ioport_resource.end = 0xDFFFFFFF; iomem_resource.start = 0xA0000000; iomem_resource.end = 0xDFFFFFFF; if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0) panic("Unable to insert PCI IOMEM resource\n"); if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0) panic("Unable to insert PCI IOPORT resource\n"); if (!pci_probe) return 0; if (pci_check_direct() < 0) { printk(KERN_WARNING "PCI: No PCI bus detected\n"); return 0; } printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", MEM_PAGING_REG); pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL); pcibios_irq_init(); pcibios_fixup_irqs(); pcibios_resource_survey(); return 0; }
/* * Initialization. Try all known PCI access methods. Note that we support * using both PCI BIOS and direct access: in such cases, we use I/O ports * to access config space, but we still keep BIOS order of cards to be * compatible with 2.0.X. This should go away some day. */ static int __init pcibios_init(void) { resource_size_t io_offset, mem_offset; LIST_HEAD(resources); struct pci_bus *bus; ioport_resource.start = 0xA0000000; ioport_resource.end = 0xDFFFFFFF; iomem_resource.start = 0xA0000000; iomem_resource.end = 0xDFFFFFFF; if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0) panic("Unable to insert PCI IOMEM resource\n"); if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0) panic("Unable to insert PCI IOPORT resource\n"); if (!pci_probe) return 0; if (pci_check_direct() < 0) { printk(KERN_WARNING "PCI: No PCI bus detected\n"); return 0; } printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", MEM_PAGING_REG); io_offset = pci_ioport_resource.start - (pci_ioport_resource.start & 0x00ffffff); mem_offset = pci_iomem_resource.start - ((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG); pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset); pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset); bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources); if (!bus) return 0; pcibios_resource_survey(); pci_bus_add_devices(bus); return 0; }
/* * Initialization. Try all known PCI access methods. Note that we support * using both PCI BIOS and direct access: in such cases, we use I/O ports * to access config space, but we still keep BIOS order of cards to be * compatible with 2.0.X. This should go away some day. */ static int __init pcibios_init(void) { ioport_resource.start = 0xA0000000; ioport_resource.end = 0xDFFFFFFF; iomem_resource.start = 0xA0000000; iomem_resource.end = 0xDFFFFFFF; if (!pci_probe) return 0; if (pci_check_direct() < 0) { printk(KERN_WARNING "PCI: No PCI bus detected\n"); return 0; } printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", MEM_PAGING_REG); { #if 0 static struct pci_bus am33_root_bus = { .children = LIST_HEAD_INIT(am33_root_bus.children), .devices = LIST_HEAD_INIT(am33_root_bus.devices), .number = 0, .secondary = 0, .resource = { &ioport_resource, &iomem_resource }, }; am33_root_bus.ops = pci_root_ops; list_add_tail(&am33_root_bus.node, &pci_root_buses); am33_root_bus.subordinate = pci_do_scan_bus(0); pci_root_bus = &am33_root_bus; #else pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL); #endif } pcibios_irq_init(); pcibios_fixup_irqs(); #if 0 pcibios_resource_survey(); #endif return 0; } arch_initcall(pcibios_init); char *__init pcibios_setup(char *str) { if (!strcmp(str, "off")) { pci_probe = 0; return NULL; } else if (!strncmp(str, "lastbus=", 8)) { pcibios_last_bus = simple_strtol(str+8, NULL, 0); return NULL; } return str; } int pcibios_enable_device(struct pci_dev *dev, int mask) { int err; err = pcibios_enable_resources(dev, mask); if (err == 0) pcibios_enable_irq(dev); return err; }