/* * Validate that the device in hand is indeed virtio network device */ static int virtio_validate_pcidev(dev_info_t *dip) { ddi_acc_handle_t pcihdl; int rc; rc = pci_config_setup(dip, &pcihdl); if (rc != DDI_SUCCESS) { return (DDI_FAILURE); } if (pci_config_get16(pcihdl, PCI_CONF_VENID) != VIRTIO_PCI_VENDOR) { cmn_err(CE_WARN, "Incorrect PCI vendor id"); rc = DDI_FAILURE; } uint16_t devid = pci_config_get16(pcihdl, PCI_CONF_DEVID); if ((devid < VIRTIO_PCI_DEVID_MIN) && (devid > VIRTIO_PCI_DEVID_MAX)) { cmn_err(CE_WARN, "Incorrect PCI device id"); rc = DDI_FAILURE; } if (pci_config_get16(pcihdl, PCI_CONF_REVID) != VIRTIO_PCI_REV_ABIV0) { cmn_err(CE_WARN, "Unsupported virtio ABI detected"); rc = DDI_FAILURE; } pci_config_teardown(&pcihdl); return (rc); }
/* * ppb_save_config_regs * * This routine saves the state of the configuration registers of all * the child nodes of each PBM. * * used by: ppb_detach() on suspends * * return value: none */ static void ppb_save_config_regs(ppb_devstate_t *ppb_p) { int i; dev_info_t *dip; ddi_acc_handle_t config_handle; for (i = 0, dip = ddi_get_child(ppb_p->dip); dip != NULL; i++, dip = ddi_get_next_sibling(dip)) { if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) { cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n", ddi_driver_name(ppb_p->dip), ddi_get_instance(ppb_p->dip), ddi_driver_name(dip), ddi_get_instance(dip)); continue; } ppb_p->config_state[i].dip = dip; ppb_p->config_state[i].command = pci_config_get16(config_handle, PCI_CONF_COMM); pci_config_teardown(&config_handle); } ppb_p->config_state_index = i; }
void load_platform_drivers(void) { dev_info_t *dip; /* dip of the isa driver */ pnode_t nodeid; /* * Install ISA driver. This is required for the southbridge IDE * workaround - to reset the IDE channel during IDE bus reset. * Panic the system in case ISA driver could not be loaded or * any problem in accessing its pci config space. Since the register * to reset the channel for IDE is in ISA config space!. */ nodeid = prom_finddevice(ONTARIO_IDE_PATHNAME); if (nodeid == OBP_BADNODE) { return; } dip = e_ddi_hold_devi_by_path(ONTARIO_ISA_PATHNAME, 0); if (dip == NULL) { cmn_err(CE_PANIC, "Could not install the isa driver\n"); return; } if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) { cmn_err(CE_PANIC, "Could not get the config space of isa\n"); return; } }
void npe_enable_htmsi_children(dev_info_t *dip) { dev_info_t *cdip = ddi_get_child(dip); ddi_acc_handle_t cfg_hdl; if (!npe_enable_htmsi_flag) return; /* * Hypertransport MSI remapping only applies to AMD CPUs using * Hypertransport (K8 and above) and not other platforms with non-AMD * CPUs that may be using Hypertransport internally in the chipset(s) */ if (!(cpuid_getvendor(CPU) == X86_VENDOR_AMD && cpuid_getfamily(CPU) >= 0xf)) return; for (; cdip != NULL; cdip = ddi_get_next_sibling(cdip)) { if (pci_config_setup(cdip, &cfg_hdl) != DDI_SUCCESS) { cmn_err(CE_NOTE, "!npe_enable_htmsi_children: " "pci_config_setup failed for %s", ddi_node_name(cdip)); return; } (void) npe_enable_htmsi(cfg_hdl); pci_config_teardown(&cfg_hdl); } }
/* * Initialize memory controller's data structure and status. */ static int fipe_mc_init(dev_info_t *dip) { ddi_acc_handle_t handle; bzero(&fipe_mc_ctrl, sizeof (fipe_mc_ctrl)); /* Hold one reference count and will be released in fipe_mc_fini. */ ndi_hold_devi(dip); /* Setup pci configuration handler. */ if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { cmn_err(CE_WARN, "!fipe: failed to setup pcicfg handler in mc_init."); ndi_rele_devi(dip); return (-1); } /* Save original configuration. */ fipe_mc_ctrl.mc_thrtctrl = pci_config_get8(handle, FIPE_MC_THRTCTRL); fipe_mc_ctrl.mc_thrtlow = pci_config_get8(handle, FIPE_MC_THRTLOW); fipe_mc_ctrl.mc_gblact = pci_config_get8(handle, FIPE_MC_GBLACT); fipe_mc_ctrl.mc_dip = dip; fipe_mc_ctrl.mc_pci_hdl = handle; fipe_mc_ctrl.mc_initialized = B_TRUE; return (0); }
/* * pcmu_init_child * * This function is called from our control ops routine on a * DDI_CTLOPS_INITCHILD request. It builds and sets the device's * parent private data area. * * used by: pcmu_ctlops() * * return value: none */ int pcmu_init_child(pcmu_t *pcmu_p, dev_info_t *child) { char name[10]; ddi_acc_handle_t config_handle; uint8_t bcr; uint8_t header_type; if (name_child(child, name, 10) != DDI_SUCCESS) return (DDI_FAILURE); ddi_set_name_addr(child, name); PCMU_DBG2(PCMU_DBG_PWR, ddi_get_parent(child), "INITCHILD: config regs setup for %s@%s\n", ddi_node_name(child), ddi_get_name_addr(child)); /* * Map the child configuration space to for initialization. * We assume the obp will do the following in the devices * config space: * * Set the latency-timer register to values appropriate * for the devices on the bus (based on other devices * MIN_GNT and MAX_LAT registers. * * Set the fast back-to-back enable bit in the command * register if it's supported and all devices on the bus * have the capability. * */ if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) { ddi_set_name_addr(child, NULL); return (DDI_FAILURE); } /* * Determine the configuration header type. */ header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); PCMU_DBG2(PCMU_DBG_INIT_CLD, pcmu_p->pcmu_dip, "%s: header_type=%x\n", ddi_driver_name(child), header_type); /* * If the device has a bus control register then program it * based on the settings in the command register. */ if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL); if (pcmu_command_default & PCI_COMM_PARITY_DETECT) bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE; if (pcmu_command_default & PCI_COMM_SERR_ENABLE) bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE; bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE; pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr); } pci_config_teardown(&config_handle); return (DDI_SUCCESS); }
/* * intercept certain interrupt services to handle special cases */ static int ppb_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result) { ddi_acc_handle_t cfg_hdl; int rv = DDI_SUCCESS; if (intr_op != DDI_INTROP_SUPPORTED_TYPES) return (i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result)); DDI_INTR_NEXDBG((CE_CONT, "ppb_intr_ops: pdip 0x%p, rdip 0x%p, op %x handle 0x%p\n", (void *)pdip, (void *)rdip, intr_op, (void *)hdlp)); /* Fixed interrupt is supported by default */ *(int *)result = DDI_INTR_TYPE_FIXED; if (ppb_support_msi == -1) { DDI_INTR_NEXDBG((CE_CONT, "ppb_intr_ops: MSI is not allowed\n")); goto OUT; } if (ppb_support_msi == 1) { DDI_INTR_NEXDBG((CE_CONT, "ppb_intr_ops: MSI is always allowed\n")); rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result); goto OUT; } if (pci_config_setup(pdip, &cfg_hdl) != DDI_SUCCESS) { DDI_INTR_NEXDBG((CE_CONT, "ppb_intr_ops: pci_config_setup() failed\n")); goto OUT; } /* * check for hypertransport msi mapping capability */ if (ppb_ht_msimap_check(cfg_hdl)) { DDI_INTR_NEXDBG((CE_CONT, "ppb_intr_ops: HT MSI mapping enabled\n")); rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result); } /* * if we add failure conditions after pci_config_setup, move this to * OUT and use an extra flag to indicate the need to teardown cfg_hdl */ pci_config_teardown(&cfg_hdl); OUT: DDI_INTR_NEXDBG((CE_CONT, "ppb_intr_ops: rdip 0x%p, returns supported types: 0x%x\n", (void *)rdip, *(int *)result)); return (rv); }
void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus, cyg_uint32 devfn, cyg_uint32 offset, cyg_uint32 data) { cyg_uint32 *pdata; pdata = pci_config_setup(bus, devfn, offset); *pdata = data; pci_config_cleanup(bus); }
/* * Examine devinfo node to determine if it is a PCI-PCI bridge * * Returns: * 0 if not a bridge or error * 1 if a bridge */ static int psm_is_pci_bridge(dev_info_t *dip) { ddi_acc_handle_t cfg_handle; int rv = 0; if (pci_config_setup(dip, &cfg_handle) == DDI_SUCCESS) { rv = ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)); pci_config_teardown(&cfg_handle); } return (rv); }
void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus, cyg_uint32 devfn, cyg_uint32 offset, cyg_uint8 data) { cyg_uint32 *pdata, mask, temp; pdata = pci_config_setup(bus, devfn, offset); mask = ~(0x000000ff << ((offset % 0x4) * 8)); temp = (cyg_uint32)(((cyg_uint32)data) << ((offset % 0x4) * 8)); *pdata = (*pdata & mask) | temp; pci_config_cleanup(bus); }
cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus, cyg_uint32 devfn, cyg_uint32 offset) { cyg_uint32 *pdata, config_data; pdata = pci_config_setup(bus, devfn, offset); config_data = *pdata; if (pci_config_cleanup(bus)) return 0xffffffff; else return config_data; }
static int agp_target_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) { agp_target_softstate_t *softstate; int instance; int status; if (cmd != DDI_ATTACH) return (DDI_FAILURE); instance = ddi_get_instance(dip); if (ddi_soft_state_zalloc(agptarget_glob_soft_handle, instance) != DDI_SUCCESS) return (DDI_FAILURE); softstate = ddi_get_soft_state(agptarget_glob_soft_handle, instance); mutex_init(&softstate->tsoft_lock, NULL, MUTEX_DRIVER, NULL); softstate->tsoft_dip = dip; status = pci_config_setup(dip, &softstate->tsoft_pcihdl); if (status != DDI_SUCCESS) { ddi_soft_state_free(agptarget_glob_soft_handle, instance); return (DDI_FAILURE); } softstate->tsoft_devid = pci_config_get32(softstate->tsoft_pcihdl, PCI_CONF_VENID); softstate->tsoft_acaptr = agp_target_cap_find(softstate->tsoft_pcihdl); if (softstate->tsoft_acaptr == 0) { /* Make a correction for some Intel chipsets */ if ((softstate->tsoft_devid & VENDOR_ID_MASK) == INTEL_VENDOR_ID) softstate->tsoft_acaptr = AGP_CAP_OFF_DEF; else return (DDI_FAILURE); } status = ddi_create_minor_node(dip, AGPTARGET_NAME, S_IFCHR, INST2NODENUM(instance), DDI_NT_AGP_TARGET, 0); if (status != DDI_SUCCESS) { pci_config_teardown(&softstate->tsoft_pcihdl); ddi_soft_state_free(agptarget_glob_soft_handle, instance); return (DDI_FAILURE); } return (DDI_SUCCESS); }
void load_platform_drivers(void) { dev_info_t *dip; /* dip of the isa driver */ /* * Install power driver which handles the power button. */ if (i_ddi_attach_hw_nodes("power") != DDI_SUCCESS) cmn_err(CE_WARN, "Failed to install \"power\" driver."); (void) ddi_hold_driver(ddi_name_to_major("power")); /* * It is OK to return error because 'us' driver is not available * in all clusters (e.g. missing in Core cluster). */ (void) i_ddi_attach_hw_nodes("us"); if (i_ddi_attach_hw_nodes("grbeep") != DDI_SUCCESS) cmn_err(CE_WARN, "Failed to install \"beep\" driver."); /* * mc-us3i must stay loaded for plat_get_mem_unum() */ if (i_ddi_attach_hw_nodes("mc-us3i") != DDI_SUCCESS) cmn_err(CE_WARN, "mc-us3i driver failed to install"); (void) ddi_hold_driver(ddi_name_to_major("mc-us3i")); /* * Install Isa driver. This is required for the southbridge IDE * workaround - to reset the IDE channel during IDE bus reset. * Panic the system in case ISA driver could not be loaded or * any problem in accessing its pci config space. Since the register * to reset the channel for IDE is in ISA config space!. */ dip = e_ddi_hold_devi_by_path(ENCHILADA_ISA_PATHNAME, 0); if (dip == NULL) { cmn_err(CE_PANIC, "Could not install the isa driver\n"); return; } if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) { cmn_err(CE_PANIC, "Could not get the config space of isa\n"); return; } }
cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus, cyg_uint32 devfn, cyg_uint32 offset) { cyg_uint32 *pdata; cyg_uint8 config_data; pdata = pci_config_setup(bus, devfn, offset); config_data = (cyg_uint8)(((*pdata) >> ((offset % 0x4) * 8)) & 0xff); if (pci_config_cleanup(bus)) return 0xff; else return config_data; }
void npe_enable_htmsi_children(dev_info_t *dip) { dev_info_t *cdip = ddi_get_child(dip); ddi_acc_handle_t cfg_hdl; for (; cdip != NULL; cdip = ddi_get_next_sibling(cdip)) { if (pci_config_setup(cdip, &cfg_hdl) != DDI_SUCCESS) { cmn_err(CE_NOTE, "!npe_enable_htmsi_children: " "pci_config_setup failed for %s", ddi_node_name(cdip)); } (void) npe_enable_htmsi(cfg_hdl); pci_config_teardown(&cfg_hdl); } }
void load_platform_drivers(void) { dev_info_t *dip; /* dip of the isa driver */ int simba_present = 0; dev_info_t *root_child_node; /* * Install Isa driver. This is required for the southbridge IDE * workaround - to reset the IDE channel during IDE bus reset. * Panic the system in case ISA driver could not be loaded or * any problem in accessing its pci config space. Since the register * to reset the channel for IDE is in ISA config space!. */ root_child_node = ddi_get_child(ddi_root_node()); while (root_child_node != NULL) { if (strcmp(ddi_node_name(root_child_node), "pci") == 0) { root_child_node = ddi_get_child(root_child_node); if (strcmp(ddi_node_name(root_child_node), "pci") == 0) simba_present = 1; break; } root_child_node = ddi_get_next_sibling(root_child_node); } if (simba_present) dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME_WITH_SIMBA, 0); else dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME, 0); if (dip == NULL) { cmn_err(CE_PANIC, "Could not install the isa driver\n"); return; } if (pci_config_setup(dip, &platform_isa_handle) != DDI_SUCCESS) { cmn_err(CE_PANIC, "Could not get the config space of isa\n"); return; } }
/* * audioixp_map_regs() * * Description: * The registers are mapped in. * * Arguments: * audioixp_state_t *state The device's state structure * * Returns: * DDI_SUCCESS Registers successfully mapped * DDI_FAILURE Registers not successfully mapped */ static int audioixp_map_regs(audioixp_state_t *statep) { dev_info_t *dip = statep->dip; /* map PCI config space */ if (pci_config_setup(statep->dip, &statep->pcih) == DDI_FAILURE) { audio_dev_warn(statep->adev, "unable to map PCI config space"); return (DDI_FAILURE); } /* map audio mixer register */ if ((ddi_regs_map_setup(dip, IXP_IO_AM_REGS, &statep->regsp, 0, 0, &dev_attr, &statep->regsh)) != DDI_SUCCESS) { audio_dev_warn(statep->adev, "unable to map audio registers"); return (DDI_FAILURE); } return (DDI_SUCCESS); }
/* * save config regs for HyperTransport devices without drivers of classes: * memory controller and hostbridge */ int npe_save_htconfig_children(dev_info_t *dip) { dev_info_t *cdip = ddi_get_child(dip); ddi_acc_handle_t cfg_hdl; uint16_t ptr; int rval = DDI_SUCCESS; uint8_t cl, scl; for (; cdip != NULL; cdip = ddi_get_next_sibling(cdip)) { if (ddi_driver_major(cdip) != DDI_MAJOR_T_NONE) continue; if (pci_config_setup(cdip, &cfg_hdl) != DDI_SUCCESS) return (DDI_FAILURE); cl = pci_config_get8(cfg_hdl, PCI_CONF_BASCLASS); scl = pci_config_get8(cfg_hdl, PCI_CONF_SUBCLASS); if (((cl == PCI_CLASS_MEM && scl == PCI_MEM_RAM) || (cl == PCI_CLASS_BRIDGE && scl == PCI_BRIDGE_HOST)) && pci_htcap_locate(cfg_hdl, 0, 0, &ptr) == DDI_SUCCESS) { if (pci_save_config_regs(cdip) != DDI_SUCCESS) { cmn_err(CE_WARN, "Failed to save HT config " "regs for %s\n", ddi_node_name(cdip)); rval = DDI_FAILURE; } else if (ddi_prop_update_int(DDI_DEV_T_NONE, cdip, "htconfig-saved", 1) != DDI_SUCCESS) { cmn_err(CE_WARN, "Failed to set htconfig-saved " "property for %s\n", ddi_node_name(cdip)); rval = DDI_FAILURE; } } pci_config_teardown(&cfg_hdl); } return (rval); }
/* * ppb_restore_config_regs * * This routine restores the state of the configuration registers of all * the child nodes of each PBM. * * used by: ppb_attach() on resume * * return value: none */ static void ppb_restore_config_regs(ppb_devstate_t *ppb_p) { int i; dev_info_t *dip; ddi_acc_handle_t config_handle; for (i = 0; i < ppb_p->config_state_index; i++) { dip = ppb_p->config_state[i].dip; if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) { cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n", ddi_driver_name(ppb_p->dip), ddi_get_instance(ppb_p->dip), ddi_driver_name(dip), ddi_get_instance(dip)); continue; } pci_config_put16(config_handle, PCI_CONF_COMM, ppb_p->config_state[i].command); pci_config_teardown(&config_handle); } }
void load_platform_drivers(void) { dev_info_t *dip; /* dip of the isa driver */ /* * Install 'us' driver. */ (void) i_ddi_attach_hw_nodes("us"); /* * mc-us3i must stay loaded for plat_get_mem_unum() */ if (i_ddi_attach_hw_nodes("mc-us3i") != DDI_SUCCESS) cmn_err(CE_WARN, "mc-us3i driver failed to install"); (void) ddi_hold_driver(ddi_name_to_major("mc-us3i")); /* * Install Isa driver. This is required for the southbridge IDE * workaround - to reset the IDE channel during IDE bus reset. * Panic the system in case ISA driver could not be loaded or * any problem in accessing its pci config space. Since the register * to reset the channel for IDE is in ISA config space!. */ dip = e_ddi_hold_devi_by_path(SCHUMACHER_ISA_PATHNAME, 0); if (dip == NULL) { cmn_err(CE_PANIC, "Could not install the isa driver\n"); return; } if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) { cmn_err(CE_PANIC, "Could not get the config space of isa\n"); return; } }
/* * audio1575_map_regs() * * Description: * The registers are mapped in. * * Arguments: * dev_info_t *dip Pointer to the device's devinfo * * Returns: * DDI_SUCCESS Registers successfully mapped * DDI_FAILURE Registers not successfully mapped */ static int audio1575_map_regs(audio1575_state_t *statep) { dev_info_t *dip = statep->dip; /* map the M1575 Audio PCI Cfg Space */ if (pci_config_setup(dip, &statep->pcih) != DDI_SUCCESS) { audio_dev_warn(statep->adev, "PCI config map failure"); goto error; } /* map the M1575 Audio registers in PCI IO Space */ if ((ddi_regs_map_setup(dip, M1575_AUDIO_IO_SPACE, &statep->regsp, 0, 0, &dev_attr, &statep->regsh)) != DDI_SUCCESS) { audio_dev_warn(statep->adev, "Audio IO mapping failure"); goto error; } return (DDI_SUCCESS); error: audio1575_unmap_regs(statep); return (DDI_FAILURE); }
/* * Autoconfiguration entry points. */ int efe_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) { ddi_acc_handle_t pci; int types; int count; int actual; uint_t pri; efe_t *efep; mac_register_t *macp; switch (cmd) { case DDI_ATTACH: break; case DDI_RESUME: efep = ddi_get_driver_private(dip); return (efe_resume(efep)); default: return (DDI_FAILURE); } /* * PCI configuration. */ if (pci_config_setup(dip, &pci) != DDI_SUCCESS) { efe_error(dip, "unable to setup PCI configuration!"); return (DDI_FAILURE); } pci_config_put16(pci, PCI_CONF_COMM, pci_config_get16(pci, PCI_CONF_COMM) | PCI_COMM_MAE | PCI_COMM_ME); pci_config_teardown(&pci); if (ddi_intr_get_supported_types(dip, &types) != DDI_SUCCESS || !(types & DDI_INTR_TYPE_FIXED)) { efe_error(dip, "fixed interrupts not supported!"); return (DDI_FAILURE); } if (ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count) != DDI_SUCCESS || count != 1) { efe_error(dip, "no fixed interrupts available!"); return (DDI_FAILURE); } /* * Initialize soft state. */ efep = kmem_zalloc(sizeof (efe_t), KM_SLEEP); ddi_set_driver_private(dip, efep); efep->efe_dip = dip; if (ddi_regs_map_setup(dip, 1, (caddr_t *)&efep->efe_regs, 0, 0, &efe_regs_acc_attr, &efep->efe_regs_acch) != DDI_SUCCESS) { efe_error(dip, "unable to setup register mapping!"); goto failure; } efep->efe_rx_ring = efe_ring_alloc(efep->efe_dip, RXDESCL); if (efep->efe_rx_ring == NULL) { efe_error(efep->efe_dip, "unable to allocate rx ring!"); goto failure; } efep->efe_tx_ring = efe_ring_alloc(efep->efe_dip, TXDESCL); if (efep->efe_tx_ring == NULL) { efe_error(efep->efe_dip, "unable to allocate tx ring!"); goto failure; } if (ddi_intr_alloc(dip, &efep->efe_intrh, DDI_INTR_TYPE_FIXED, 0, count, &actual, DDI_INTR_ALLOC_STRICT) != DDI_SUCCESS || actual != count) { efe_error(dip, "unable to allocate fixed interrupt!"); goto failure; } if (ddi_intr_get_pri(efep->efe_intrh, &pri) != DDI_SUCCESS || pri >= ddi_intr_get_hilevel_pri()) { efe_error(dip, "unable to get valid interrupt priority!"); goto failure; } mutex_init(&efep->efe_intrlock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(pri)); mutex_init(&efep->efe_txlock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(pri)); /* * Initialize device. */ mutex_enter(&efep->efe_intrlock); mutex_enter(&efep->efe_txlock); efe_reset(efep); mutex_exit(&efep->efe_txlock); mutex_exit(&efep->efe_intrlock); /* Use factory address as default */ efe_getaddr(efep, efep->efe_macaddr); /* * Enable the ISR. */ if (ddi_intr_add_handler(efep->efe_intrh, efe_intr, efep, NULL) != DDI_SUCCESS) { efe_error(dip, "unable to add interrupt handler!"); goto failure; } if (ddi_intr_enable(efep->efe_intrh) != DDI_SUCCESS) { efe_error(dip, "unable to enable interrupt!"); goto failure; } /* * Allocate MII resources. */ if ((efep->efe_miih = mii_alloc(efep, dip, &efe_mii_ops)) == NULL) { efe_error(dip, "unable to allocate mii resources!"); goto failure; } /* * Allocate MAC resources. */ if ((macp = mac_alloc(MAC_VERSION)) == NULL) { efe_error(dip, "unable to allocate mac resources!"); goto failure; } macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; macp->m_driver = efep; macp->m_dip = dip; macp->m_src_addr = efep->efe_macaddr; macp->m_callbacks = &efe_m_callbacks; macp->m_min_sdu = 0; macp->m_max_sdu = ETHERMTU; macp->m_margin = VLAN_TAGSZ; if (mac_register(macp, &efep->efe_mh) != 0) { efe_error(dip, "unable to register with mac!"); goto failure; } mac_free(macp); ddi_report_dev(dip); return (DDI_SUCCESS); failure: if (macp != NULL) { mac_free(macp); } if (efep->efe_miih != NULL) { mii_free(efep->efe_miih); } if (efep->efe_intrh != NULL) { (void) ddi_intr_disable(efep->efe_intrh); (void) ddi_intr_remove_handler(efep->efe_intrh); (void) ddi_intr_free(efep->efe_intrh); } mutex_destroy(&efep->efe_txlock); mutex_destroy(&efep->efe_intrlock); if (efep->efe_tx_ring != NULL) { efe_ring_free(&efep->efe_tx_ring); } if (efep->efe_rx_ring != NULL) { efe_ring_free(&efep->efe_rx_ring); } if (efep->efe_regs_acch != NULL) { ddi_regs_map_free(&efep->efe_regs_acch); } kmem_free(efep, sizeof (efe_t)); return (DDI_FAILURE); }
/* * attach entry point: * * normal attach: * * create soft state structure (dip, reg, nreg and state fields) * map in configuration header * make sure device is properly configured * report device */ static int pmubus_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) { pmubus_devstate_t *pmubusp; /* per pmubus state pointer */ int32_t instance; switch (cmd) { case DDI_ATTACH: /* * Allocate soft state for this instance. */ instance = ddi_get_instance(dip); if (ddi_soft_state_zalloc(per_pmubus_state, instance) != DDI_SUCCESS) { cmn_err(CE_WARN, "pmubus_attach: Can't allocate soft " "state.\n"); goto fail_exit; } pmubusp = ddi_get_soft_state(per_pmubus_state, instance); pmubusp->pmubus_dip = dip; /* Cache our register property */ if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", (caddr_t)&pmubusp->pmubus_regp, &pmubusp->pmubus_reglen) != DDI_SUCCESS) { cmn_err(CE_WARN, "pmubus_attach: Can't acquire reg " "property.\n"); goto fail_get_regs; } /* Cache our ranges property */ if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", (caddr_t)&pmubusp->pmubus_rangep, &pmubusp->pmubus_rnglen) != DDI_SUCCESS) { cmn_err(CE_WARN, "pmubus_attach: Can't acquire the " "ranges property.\n"); goto fail_get_ranges; } /* Calculate the number of ranges */ pmubusp->pmubus_nranges = pmubusp->pmubus_rnglen / sizeof (pmu_rangespec_t); /* Set up the mapping to our registers */ if (pci_config_setup(dip, &pmubusp->pmubus_reghdl) != DDI_SUCCESS) { cmn_err(CE_WARN, "pmubus_attach: Can't map in " "register space.\n"); goto fail_map_regs; } /* Initialize our register access mutex */ mutex_init(&pmubusp->pmubus_reg_access_lock, NULL, MUTEX_DRIVER, NULL); ddi_report_dev(dip); return (DDI_SUCCESS); case DDI_RESUME: return (DDI_SUCCESS); } fail_map_regs: kmem_free(pmubusp->pmubus_rangep, pmubusp->pmubus_rnglen); fail_get_ranges: kmem_free(pmubusp->pmubus_regp, pmubusp->pmubus_reglen); fail_get_regs: ddi_soft_state_free(per_pmubus_state, instance); fail_exit: return (DDI_FAILURE); }
static void gfxp_check_for_console(dev_info_t *devi, struct vgatext_softc *softc, int pci_pcie_bus) { ddi_acc_handle_t pci_conf; dev_info_t *pdevi; uint16_t data16; /* * Based on Section 11.3, "PCI Display Subsystem Initialization", * of the 1.1 PCI-to-PCI Bridge Architecture Specification * determine if this is the boot console device. First, see * if the SBIOS has turned on PCI I/O for this device. Then if * this is PCI/PCI-E, verify the parent bridge has VGAEnable set. */ if (pci_config_setup(devi, &pci_conf) != DDI_SUCCESS) { cmn_err(CE_WARN, MYNAME ": can't get PCI conf handle"); return; } data16 = pci_config_get16(pci_conf, PCI_CONF_COMM); if (data16 & PCI_COMM_IO) softc->flags |= GFXP_FLAG_CONSOLE; pci_config_teardown(&pci_conf); /* If IO not enabled or ISA/EISA, just return */ if (!(softc->flags & GFXP_FLAG_CONSOLE) || !pci_pcie_bus) return; /* * Check for VGA Enable in the Bridge Control register for all * PCI/PCIEX parents. If not set all the way up the chain, * this cannot be the boot console. */ pdevi = ddi_get_parent(devi); while (pdevi) { int error; ddi_acc_handle_t ppci_conf; char *parent_type = NULL; error = ddi_prop_lookup_string(DDI_DEV_T_ANY, pdevi, DDI_PROP_DONTPASS, "device_type", &parent_type); if (error != DDI_SUCCESS) { return; } /* Verify still on the PCI/PCIEX parent tree */ if (!STREQ(parent_type, "pci") && !STREQ(parent_type, "pciex")) { ddi_prop_free(parent_type); return; } ddi_prop_free(parent_type); parent_type = NULL; if (pci_config_setup(pdevi, &ppci_conf) != DDI_SUCCESS) { /* No registers on root node, done with check */ return; } data16 = pci_config_get16(ppci_conf, PCI_BCNF_BCNTRL); pci_config_teardown(&ppci_conf); if (!(data16 & PCI_BCNF_BCNTRL_VGA_ENABLE)) { softc->flags &= ~GFXP_FLAG_CONSOLE; return; } pdevi = ddi_get_parent(pdevi); } }
/** * Attach entry point, to attach a device to the system or resume it. * * @param pDip The module structure instance. * @param enmCmd Attach type (ddi_attach_cmd_t) * * @return corresponding solaris error code. */ static int VBoxGuestSolarisAttach(dev_info_t *pDip, ddi_attach_cmd_t enmCmd) { LogFlow((DEVICE_NAME "::Attach\n")); switch (enmCmd) { case DDI_ATTACH: { if (g_pDip) { LogRel((DEVICE_NAME "::Attach: Only one instance supported.\n")); return DDI_FAILURE; } int instance = ddi_get_instance(pDip); /* * Enable resources for PCI access. */ ddi_acc_handle_t PciHandle; int rc = pci_config_setup(pDip, &PciHandle); if (rc == DDI_SUCCESS) { /* * Map the register address space. */ caddr_t baseAddr; ddi_device_acc_attr_t deviceAttr; deviceAttr.devacc_attr_version = DDI_DEVICE_ATTR_V0; deviceAttr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; deviceAttr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; deviceAttr.devacc_attr_access = DDI_DEFAULT_ACC; rc = ddi_regs_map_setup(pDip, 1, &baseAddr, 0, 0, &deviceAttr, &g_PciIOHandle); if (rc == DDI_SUCCESS) { /* * Read size of the MMIO region. */ g_uIOPortBase = (uintptr_t)baseAddr; rc = ddi_dev_regsize(pDip, 2, &g_cbMMIO); if (rc == DDI_SUCCESS) { rc = ddi_regs_map_setup(pDip, 2, &g_pMMIOBase, 0, g_cbMMIO, &deviceAttr, &g_PciMMIOHandle); if (rc == DDI_SUCCESS) { /* * Add IRQ of VMMDev. */ rc = VBoxGuestSolarisAddIRQ(pDip); if (rc == DDI_SUCCESS) { /* * Call the common device extension initializer. */ rc = VBoxGuestInitDevExt(&g_DevExt, g_uIOPortBase, g_pMMIOBase, g_cbMMIO, #if ARCH_BITS == 64 VBOXOSTYPE_Solaris_x64, #else VBOXOSTYPE_Solaris, #endif VMMDEV_EVENT_MOUSE_POSITION_CHANGED); if (RT_SUCCESS(rc)) { rc = ddi_create_minor_node(pDip, DEVICE_NAME, S_IFCHR, instance, DDI_PSEUDO, 0); if (rc == DDI_SUCCESS) { g_pDip = pDip; pci_config_teardown(&PciHandle); return DDI_SUCCESS; } LogRel((DEVICE_NAME "::Attach: ddi_create_minor_node failed.\n")); VBoxGuestDeleteDevExt(&g_DevExt); } else LogRel((DEVICE_NAME "::Attach: VBoxGuestInitDevExt failed.\n")); VBoxGuestSolarisRemoveIRQ(pDip); } else LogRel((DEVICE_NAME "::Attach: VBoxGuestSolarisAddIRQ failed.\n")); ddi_regs_map_free(&g_PciMMIOHandle); } else LogRel((DEVICE_NAME "::Attach: ddi_regs_map_setup for MMIO region failed.\n")); } else LogRel((DEVICE_NAME "::Attach: ddi_dev_regsize for MMIO region failed.\n")); ddi_regs_map_free(&g_PciIOHandle); } else LogRel((DEVICE_NAME "::Attach: ddi_regs_map_setup for IOport failed.\n")); pci_config_teardown(&PciHandle); } else LogRel((DEVICE_NAME "::Attach: pci_config_setup failed rc=%d.\n", rc)); return DDI_FAILURE; } case DDI_RESUME: { /** @todo implement resume for guest driver. */ return DDI_SUCCESS; } default: return DDI_FAILURE; } }
int pcn_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) { pcn_t *pcnp; mac_register_t *macp; const pcn_type_t *pcn_type; int instance = ddi_get_instance(dip); int rc; ddi_acc_handle_t pci; uint16_t venid; uint16_t devid; uint16_t svid; uint16_t ssid; switch (cmd) { case DDI_RESUME: return (pcn_ddi_resume(dip)); case DDI_ATTACH: break; default: return (DDI_FAILURE); } if (ddi_slaveonly(dip) == DDI_SUCCESS) { pcn_error(dip, "slot does not support PCI bus-master"); return (DDI_FAILURE); } if (ddi_intr_hilevel(dip, 0) != 0) { pcn_error(dip, "hilevel interrupts not supported"); return (DDI_FAILURE); } if (pci_config_setup(dip, &pci) != DDI_SUCCESS) { pcn_error(dip, "unable to setup PCI config handle"); return (DDI_FAILURE); } venid = pci_config_get16(pci, PCI_CONF_VENID); devid = pci_config_get16(pci, PCI_CONF_DEVID); svid = pci_config_get16(pci, PCI_CONF_SUBVENID); ssid = pci_config_get16(pci, PCI_CONF_SUBSYSID); if ((pcn_type = pcn_match(venid, devid)) == NULL) { pci_config_teardown(&pci); pcn_error(dip, "Unable to identify PCI card"); return (DDI_FAILURE); } if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model", pcn_type->pcn_name) != DDI_PROP_SUCCESS) { pci_config_teardown(&pci); pcn_error(dip, "Unable to create model property"); return (DDI_FAILURE); } if (ddi_soft_state_zalloc(pcn_ssp, instance) != DDI_SUCCESS) { pcn_error(dip, "Unable to allocate soft state"); pci_config_teardown(&pci); return (DDI_FAILURE); } pcnp = ddi_get_soft_state(pcn_ssp, instance); pcnp->pcn_dip = dip; pcnp->pcn_instance = instance; pcnp->pcn_extphyaddr = -1; if (ddi_get_iblock_cookie(dip, 0, &pcnp->pcn_icookie) != DDI_SUCCESS) { pcn_error(pcnp->pcn_dip, "ddi_get_iblock_cookie failed"); ddi_soft_state_free(pcn_ssp, instance); pci_config_teardown(&pci); return (DDI_FAILURE); } mutex_init(&pcnp->pcn_xmtlock, NULL, MUTEX_DRIVER, pcnp->pcn_icookie); mutex_init(&pcnp->pcn_intrlock, NULL, MUTEX_DRIVER, pcnp->pcn_icookie); mutex_init(&pcnp->pcn_reglock, NULL, MUTEX_DRIVER, pcnp->pcn_icookie); /* * Enable bus master, IO space, and memory space accesses */ pci_config_put16(pci, PCI_CONF_COMM, pci_config_get16(pci, PCI_CONF_COMM) | PCI_COMM_ME | PCI_COMM_MAE); pci_config_teardown(&pci); if (ddi_regs_map_setup(dip, 1, (caddr_t *)&pcnp->pcn_regs, 0, 0, &pcn_devattr, &pcnp->pcn_regshandle)) { pcn_error(dip, "ddi_regs_map_setup failed"); goto fail; } if (pcn_set_chipid(pcnp, (uint32_t)ssid << 16 | (uint32_t)svid) != DDI_SUCCESS) { goto fail; } if ((pcnp->pcn_mii = mii_alloc(pcnp, dip, &pcn_mii_ops)) == NULL) goto fail; /* XXX: need to set based on device */ mii_set_pauseable(pcnp->pcn_mii, B_FALSE, B_FALSE); if ((pcn_allocrxring(pcnp) != DDI_SUCCESS) || (pcn_alloctxring(pcnp) != DDI_SUCCESS)) { pcn_error(dip, "unable to allocate DMA resources"); goto fail; } pcnp->pcn_promisc = B_FALSE; mutex_enter(&pcnp->pcn_intrlock); mutex_enter(&pcnp->pcn_xmtlock); rc = pcn_initialize(pcnp, B_TRUE); mutex_exit(&pcnp->pcn_xmtlock); mutex_exit(&pcnp->pcn_intrlock); if (rc != DDI_SUCCESS) goto fail; if (ddi_add_intr(dip, 0, NULL, NULL, pcn_intr, (caddr_t)pcnp) != DDI_SUCCESS) { pcn_error(dip, "unable to add interrupt"); goto fail; } pcnp->pcn_flags |= PCN_INTR_ENABLED; if ((macp = mac_alloc(MAC_VERSION)) == NULL) { pcn_error(pcnp->pcn_dip, "mac_alloc failed"); goto fail; } macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; macp->m_driver = pcnp; macp->m_dip = dip; macp->m_src_addr = pcnp->pcn_addr; macp->m_callbacks = &pcn_m_callbacks; macp->m_min_sdu = 0; macp->m_max_sdu = ETHERMTU; macp->m_margin = VLAN_TAGSZ; if (mac_register(macp, &pcnp->pcn_mh) == DDI_SUCCESS) { mac_free(macp); return (DDI_SUCCESS); } mac_free(macp); return (DDI_SUCCESS); fail: pcn_teardown(pcnp); return (DDI_FAILURE); }
void load_platform_drivers(void) { extern int watchdog_available; extern int watchdog_enable; dev_info_t *dip; /* dip of the isa driver */ int simba_present = 0; dev_info_t *root_child_node; major_t major; if (ddi_install_driver("power") != DDI_SUCCESS) cmn_err(CE_WARN, "Failed to install \"power\" driver."); /* * Install Isa driver. This is required for the southbridge IDE * workaround - to reset the IDE channel during IDE bus reset. * Panic the system in case ISA driver could not be loaded or * any problem in accessing its pci config space. Since the register * to reset the channel for IDE is in ISA config space!. */ root_child_node = ddi_get_child(ddi_root_node()); while (root_child_node != NULL) { if (strcmp(ddi_node_name(root_child_node), "pci") == 0) { root_child_node = ddi_get_child(root_child_node); if (strcmp(ddi_node_name(root_child_node), "pci") == 0) simba_present = 1; break; } root_child_node = ddi_get_next_sibling(root_child_node); } if (simba_present) dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME_WITH_SIMBA, 0); else dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME, 0); if (dip == NULL) { cmn_err(CE_PANIC, "Could not install the isa driver\n"); return; } if (pci_config_setup(dip, &platform_isa_handle) != DDI_SUCCESS) { cmn_err(CE_PANIC, "Could not get the config space of isa\n"); return; } /* * Load the blade support chip driver. * */ if (((major = ddi_name_to_major(BSC_DRV)) == -1) || (ddi_hold_installed_driver(major) == NULL)) { cmn_err(CE_WARN, "%s: failed to load", BSC_DRV); } else { bsc_drv_func_ptr = (void (*)(struct bscv_idi_info *)) modgetsymvalue(BSC_DRV_FUNC, 0); if (bsc_drv_func_ptr == NULL) { cmn_err(CE_WARN, "load_platform_defaults: %s()" " not found; signatures will not be updated\n", BSC_DRV_FUNC); watchdog_available = 0; if (watchdog_enable) { cmn_err(CE_WARN, "load_platform_defaults: %s()" " not found; BSC OS watchdog service not available\n", BSC_DRV_FUNC); } } } }
/* * The VGA device could be under a subtractive PCI bridge on some systems. * Though the PCI_BCNF_BCNTRL_VGA_ENABLE bit is not set on such subtractive * PCI bridge, the subtractive PCI bridge can forward VGA access if no other * agent claims the access. * The vga_enable element in param acts as a flag, if not set, ignore the * checking for the PCI_BCNF_BCNTRL_VGA_ENABLE bit of the PCI bridge during * the search. */ static int find_fb_dev(dev_info_t *dip, void *param) { struct find_fb_dev_param *p = param; char *dev_type; dev_info_t *pdip; char *parent_type; if (dip == ddi_root_node()) return (DDI_WALK_CONTINUE); if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "device_type", &dev_type) != DDI_SUCCESS) return (DDI_WALK_PRUNECHILD); if ((strcmp(dev_type, "isa") == 0) || (strcmp(dev_type, "eisa") == 0)) { ddi_prop_free(dev_type); return (DDI_WALK_CONTINUE); } if ((strcmp(dev_type, "pci") == 0) || (strcmp(dev_type, "pciex") == 0)) { ddi_acc_handle_t pci_conf; uint16_t data16; char *nodename; ddi_prop_free(dev_type); if (!p->vga_enable) return (DDI_WALK_CONTINUE); nodename = ddi_node_name(dip); /* * If the node is not a PCI-to-PCI bridge, continue traversing * (it could be the root node), otherwise, check for the * VGAEnable bit to be set in the Bridge Control Register. */ if (strcmp(nodename, "pci") == 0) { if (is_pci_bridge(dip) == B_FALSE) return (DDI_WALK_CONTINUE); } if (i_ddi_attach_node_hierarchy(dip) != DDI_SUCCESS) return (DDI_WALK_PRUNECHILD); if (pci_config_setup(dip, &pci_conf) != DDI_SUCCESS) return (DDI_WALK_PRUNECHILD); data16 = pci_config_get16(pci_conf, PCI_BCNF_BCNTRL); pci_config_teardown(&pci_conf); if (data16 & PCI_BCNF_BCNTRL_VGA_ENABLE) return (DDI_WALK_CONTINUE); return (DDI_WALK_PRUNECHILD); } if (strcmp(dev_type, "display") != 0) { ddi_prop_free(dev_type); return (DDI_WALK_CONTINUE); } ddi_prop_free(dev_type); if ((pdip = ddi_get_parent(dip)) == NULL) return (DDI_WALK_PRUNECHILD); if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, "device_type", &parent_type) != DDI_SUCCESS) return (DDI_WALK_PRUNECHILD); if ((strcmp(parent_type, "isa") == 0) || (strcmp(parent_type, "eisa") == 0)) { p->found_dip = dip; ddi_prop_free(parent_type); return (DDI_WALK_TERMINATE); } if ((strcmp(parent_type, "pci") == 0) || (strcmp(parent_type, "pciex") == 0)) { ddi_acc_handle_t pci_conf; uint16_t data16; ddi_prop_free(parent_type); if (i_ddi_attach_node_hierarchy(dip) != DDI_SUCCESS) return (DDI_WALK_PRUNECHILD); if (pci_config_setup(dip, &pci_conf) != DDI_SUCCESS) return (DDI_WALK_PRUNECHILD); data16 = pci_config_get16(pci_conf, PCI_CONF_COMM); pci_config_teardown(&pci_conf); if (!(data16 & PCI_COMM_IO)) return (DDI_WALK_PRUNECHILD); p->found_dip = dip; return (DDI_WALK_TERMINATE); } ddi_prop_free(parent_type); return (DDI_WALK_PRUNECHILD); }
/* * Controller specific initialization */ uint_t sil3xxx_init_controller(dev_info_t *dip, /* LINTED */ ushort_t vendor_id, ushort_t device_id) { ddi_acc_handle_t pci_conf_handle; /* pci config space handle */ uint8_t cache_lnsz, frrc = 0; uint32_t fifo_cnt_ctl; int ports, i; #ifdef DEBUG /* LINTED */ ushort_t sfiscfg_val; #endif /* * Sil3114, Sil3512, Sil3112 * We want to perform this initialization only once per entire * pciide controller (all channels) */ if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_get_parent(dip), DDI_PROP_DONTPASS, "sil3xxx-initialized")) { return (TRUE); } if (pci_config_setup(ddi_get_parent(dip), &pci_conf_handle) != DDI_SUCCESS) { cmn_err(CE_WARN, "sil3xxx_init_controller: Can't do pci_config_setup\n"); return (FALSE); } /* * Sil3114/3512/3112 incorrectly change between MR and back to * MRM for same transaction, which violates the PCI spec and can * lead to incorrect data reads. The workaround * is to set bits 2:0 in the FIFO count and control register so * that its value, a multiple of 32 bytes starting at 32, not 0, * is greater or equal to the cacheline size, a multiple of 4 * bytes. This will prevent any reads until the FIFO free space * is greater than a cacheline size, ensuring only MRM is issued. */ cache_lnsz = pci_config_get8(pci_conf_handle, PCI_CONF_CACHE_LINESZ); /* * The cache line is specified in 32-bit words, so multiply by 4 * to get bytes. Then divide by 32 bytes, the granularity of the * FIFO control bits 2:0. Add 1 if there is any remainder to * account for a partial 32-byte block, then subtract 1 since for * FIFO controls bits 2:0, 0 corresponds to 32, 1 corresponds to * 64, and so on. The calculation is expanded for clarity. */ if (cache_lnsz != 0) { frrc = (cache_lnsz * 4 / 32) + (((cache_lnsz * 4) % 32) ? 1 : 0) - 1; } if (device_id == SIL3114_DEVICE_ID) { ports = 4; } else { ports = 2; } /* * The following BAR5 registers are accessed via an indirect register * in the PCI configuration space rather than mapping BAR5. */ for (i = 0; i < ports; i++) { GET_BAR5_INDIRECT(pci_conf_handle, fifocntctl[i], fifo_cnt_ctl); fifo_cnt_ctl = (fifo_cnt_ctl & ~0x7) | (frrc & 0x7); PUT_BAR5_INDIRECT(pci_conf_handle, fifocntctl[i], fifo_cnt_ctl); /* * Correct default setting for FIS0cfg */ #ifdef DEBUG GET_BAR5_INDIRECT(pci_conf_handle, sfiscfg[i], sfiscfg_val); ADBG_WARN(("sil3xxx_init_controller: old val SFISCfg " "ch%d: %x\n", i, sfiscfg_val)); #endif PUT_BAR5_INDIRECT(pci_conf_handle, sfiscfg[i], SFISCFG_ERRATA); #ifdef DEBUG GET_BAR5_INDIRECT(pci_conf_handle, sfiscfg[i], sfiscfg_val); ADBG_WARN(("sil3xxx_init_controller: new val SFISCfg " "ch%d: %x\n", i, sfiscfg_val)); #endif } /* Now tear down the pci config setup */ pci_config_teardown(&pci_conf_handle); /* Create property indicating that initialization was done */ (void) ddi_prop_update_int(DDI_DEV_T_NONE, ddi_get_parent(dip), "sil3xxx-initialized", 1); return (TRUE); }
static int acebus_config(ebus_devstate_t *ebus_p) { ddi_acc_handle_t conf_handle; uint16_t comm; #ifdef ACEBUS_HOTPLUG int tcr_reg; caddr_t csr_io; ddi_device_acc_attr_t csr_attr = { /* CSR map attributes */ DDI_DEVICE_ATTR_V0, DDI_STRUCTURE_LE_ACC, DDI_STRICTORDER_ACC }; ddi_acc_handle_t csr_handle; #endif /* * Make sure the master enable and memory access enable * bits are set in the config command register. */ if (pci_config_setup(ebus_p->dip, &conf_handle) != DDI_SUCCESS) return (0); comm = pci_config_get16(conf_handle, PCI_CONF_COMM), #ifdef DEBUG DBG1(D_ATTACH, ebus_p, "command register was 0x%x\n", comm); #endif comm |= (PCI_COMM_ME|PCI_COMM_MAE|PCI_COMM_SERR_ENABLE| PCI_COMM_PARITY_DETECT); pci_config_put16(conf_handle, PCI_CONF_COMM, comm), #ifdef DEBUG DBG1(D_MAP, ebus_p, "command register is now 0x%x\n", pci_config_get16(conf_handle, PCI_CONF_COMM)); #endif pci_config_put8(conf_handle, PCI_CONF_CACHE_LINESZ, (uchar_t)acebus_cache_line_size); pci_config_put8(conf_handle, PCI_CONF_LATENCY_TIMER, (uchar_t)acebus_latency_timer); pci_config_teardown(&conf_handle); #ifdef ACEBUS_HOTPLUG if (acebus_update_props(ebus_p) != DDI_SUCCESS) { cmn_err(CE_WARN, "%s%d: Could not update special properties.", ddi_driver_name(ebus_p->dip), ddi_get_instance(ebus_p->dip)); return (0); } if (ddi_regs_map_setup(ebus_p->dip, CSR_IO_RINDEX, (caddr_t *)&csr_io, 0, CSR_SIZE, &csr_attr, &csr_handle) != DDI_SUCCESS) { cmn_err(CE_WARN, "%s%d: Could not map Ebus CSR.", ddi_driver_name(ebus_p->dip), ddi_get_instance(ebus_p->dip)); } #ifdef DEBUG if (acebus_debug_flags) { DBG3(D_ATTACH, ebus_p, "tcr[123] = %x,%x,%x\n", ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR1_OFF)), ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR2_OFF)), ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR3_OFF))); DBG2(D_ATTACH, ebus_p, "pmd-aux=%x, freq-aux=%x\n", ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + PMD_AUX_OFF)), ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + FREQ_AUX_OFF))); #ifdef ACEBUS_DEBUG for (comm = 0; comm < 4; comm++) prom_printf("dcsr%d=%x, dacr%d=%x, dbcr%d=%x\n", comm, ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + 0x700000+(0x2000*comm))), comm, ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + 0x700000+(0x2000*comm)+4)), comm, ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + 0x700000+(0x2000*comm)+8))); #endif } /* acebus_debug_flags */ #endif /* If TCR registers are not initialized, initialize them here */ tcr_reg = ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR1_OFF)); if ((tcr_reg == 0) || (tcr_reg == -1)) ddi_put32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR1_OFF), TCR1_REGVAL); tcr_reg = ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR2_OFF)); if ((tcr_reg == 0) || (tcr_reg == -1)) ddi_put32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR2_OFF), TCR2_REGVAL); tcr_reg = ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR3_OFF)); if ((tcr_reg == 0) || (tcr_reg == -1)) ddi_put32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR3_OFF), TCR3_REGVAL); #ifdef DEBUG if (acebus_debug_flags) { DBG3(D_ATTACH, ebus_p, "wrote tcr[123] = %x,%x,%x\n", ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR1_OFF)), ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR2_OFF)), ddi_get32(csr_handle, (uint32_t *)((caddr_t)csr_io + TCR3_OFF))); } #endif ddi_regs_map_free(&csr_handle); #endif /* ACEBUS_HOTPLUG */ return (1); /* return success */ }